diff --git a/compiler/aggas.pas b/compiler/aggas.pas
index bcf00ded31..637763cb57 100644
--- a/compiler/aggas.pas
+++ b/compiler/aggas.pas
@@ -199,7 +199,7 @@ implementation
            (atype<>sec_toc) and
            (atype<>sec_user) and
            { on embedded systems every byte counts, so smartlink bss too }
-           ((atype<>sec_bss) or (target_info.system in systems_embedded));
+           ((atype<>sec_bss) or (target_info.system in (systems_embedded+systems_freertos)));
       end;
 
     function TGNUAssembler.sectionname(atype:TAsmSectiontype;const aname:string;aorder:TAsmSectionOrder):string;
diff --git a/compiler/arm/agarmgas.pas b/compiler/arm/agarmgas.pas
index a24f9365cf..e51b715f41 100644
--- a/compiler/arm/agarmgas.pas
+++ b/compiler/arm/agarmgas.pas
@@ -442,7 +442,7 @@ unit agarmgas;
             asmbin : 'as';
             asmcmd : '-o $OBJ $EXTRAOPT $ASM';
             supported_targets : [system_arm_linux,system_arm_netbsd,system_arm_wince,system_arm_gba,system_arm_palmos,system_arm_nds,
-                                 system_arm_embedded,system_arm_symbian,system_arm_android,system_arm_aros];
+                                 system_arm_embedded,system_arm_symbian,system_arm_android,system_arm_aros,system_arm_freertos];
             flags : [af_needar,af_smartlink_sections];
             labelprefix : '.L';
             comment : '# ';
diff --git a/compiler/arm/cpuelf.pas b/compiler/arm/cpuelf.pas
index ad48f706e4..311b5144f0 100644
--- a/compiler/arm/cpuelf.pas
+++ b/compiler/arm/cpuelf.pas
@@ -974,7 +974,7 @@ implementation
          supported_targets : [system_arm_embedded,system_arm_darwin,
                               system_arm_linux,system_arm_netbsd,
                               system_arm_gba,system_arm_nds,
-                              system_arm_aros];
+                              system_arm_aros,system_arm_freertos];
          flags : [af_outputbinary,af_smartlink_sections,af_supports_dwarf];
          labelprefix : '.L';
          comment : '';
diff --git a/compiler/arm/cpuinfo.pas b/compiler/arm/cpuinfo.pas
index 5f809a5ef9..49c0115c7a 100644
--- a/compiler/arm/cpuinfo.pas
+++ b/compiler/arm/cpuinfo.pas
@@ -82,6 +82,7 @@ Type
      );
 
 Const
+
   fputypestrllvm : array[tfputype] of string[15] = ('',
     '',
     '',
@@ -347,6 +348,9 @@ Type
       ct_stm32f756xe,
       ct_stm32f756xg,
 
+      ct_stm32g071rb,
+      ct_nucleog071rb,
+
       { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
       ct_lm3s1110,
       ct_lm3s1133,
@@ -819,8 +823,8 @@ Const
       (controllertypestr:'STM32F401RD';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00018000),
       (controllertypestr:'STM32F401VD';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00018000),
       (controllertypestr:'STM32F401CE';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000),
-      (controllertypestr:'STM32F401RE';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000),
-      (controllertypestr:'NUCLEOF401RE';    controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000),
+      (controllertypestr:'STM32F401RE';     controllerunitstr:'STM32F401XE';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000),
+      (controllertypestr:'NUCLEOF401RE';    controllerunitstr:'STM32F401XE';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000),
       (controllertypestr:'STM32F401VE';     controllerunitstr:'STM32F401XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00018000),
       (controllertypestr:'STM32F407VG';     controllerunitstr:'STM32F407XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00020000),
       (controllertypestr:'DISCOVERYF407VG'; controllerunitstr:'STM32F407XX';      cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00020000),
@@ -870,6 +874,9 @@ Const
       (controllertypestr:'STM32F756XE';     controllerunitstr:'STM32F756';        cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00080000; srambase:$20010000; sramsize:$00040000),
       (controllertypestr:'STM32F756XG';     controllerunitstr:'STM32F756';        cputype:cpu_armv7em; fputype:fpu_soft; flashbase:$08000000; flashsize:$00100000; srambase:$20010000; sramsize:$00040000),
 
+      (controllertypestr:'STM32G071RB'         ; controllerunitstr:'STM32G071XX'         ; cputype:cpu_armv6m; fputype:fpu_soft; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00009000),
+      (controllertypestr:'NUCLEOG071RB'        ; controllerunitstr:'STM32G071XX'         ; cputype:cpu_armv6m; fputype:fpu_soft; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00009000),
+
       (controllertypestr:'LM3S1110';	controllerunitstr:'LM3FURY';	cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00010000;	srambase:$20000000;	sramsize:$00004000),
       (controllertypestr:'LM3S1133';	controllerunitstr:'LM3FURY';	cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00010000;	srambase:$20000000;	sramsize:$00004000),
       (controllertypestr:'LM3S1138';	controllerunitstr:'LM3FURY';	cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00000000;	flashsize:$00010000;	srambase:$20000000;	sramsize:$00004000),
diff --git a/compiler/arm/cputarg.pas b/compiler/arm/cputarg.pas
index 5d5e280729..5e3f3c31a6 100644
--- a/compiler/arm/cputarg.pas
+++ b/compiler/arm/cputarg.pas
@@ -68,6 +68,10 @@ implementation
     {$ifndef NOTARGETAROS}
       ,t_aros
     {$endif}
+    {$ifndef NOTARGETFREERTOS}
+      ,t_freertos
+    {$endif}
+
 
 {**************************************
              Assemblers
diff --git a/compiler/options.pas b/compiler/options.pas
index 70b178fbb7..4c111ea56d 100644
--- a/compiler/options.pas
+++ b/compiler/options.pas
@@ -3940,7 +3940,7 @@ begin
     end;
 
   { Set up default value for the heap }
-  if target_info.system in systems_embedded then
+  if target_info.system in (systems_embedded+systems_freertos) then
     begin
       case target_info.system of
 {$ifdef AVR}
@@ -3950,6 +3950,8 @@ begin
           else
             heapsize:=128;
 {$endif AVR}
+        system_arm_freertos:
+          heapsize:=8192;
         system_arm_embedded:
           heapsize:=256;
         system_mipsel_embedded:
diff --git a/compiler/systems.inc b/compiler/systems.inc
index 1fed2fc62e..218b14078d 100644
--- a/compiler/systems.inc
+++ b/compiler/systems.inc
@@ -193,7 +193,8 @@
              system_x86_64_haiku,       { 102 }
              system_xtensa_embedded,    { 103 }
              system_xtensa_freertos,    { 104 }
-             system_xtensa_linux        { 105 }
+             system_xtensa_linux,       { 105 }
+             system_arm_freertos        { 106 }
        );
 
      type
diff --git a/compiler/systems.pas b/compiler/systems.pas
index cdd5b9a057..05042881ec 100644
--- a/compiler/systems.pas
+++ b/compiler/systems.pas
@@ -305,7 +305,7 @@ interface
                            system_xtensa_embedded];
 
        { all FreeRTOS systems }
-       systems_freertos = [system_xtensa_freertos];
+       systems_freertos = [system_xtensa_freertos,system_arm_freertos];
 
        { all systems that allow section directive }
        systems_allow_section = systems_embedded;
diff --git a/compiler/systems/i_freertos.pas b/compiler/systems/i_freertos.pas
index a36c696e29..6715da2ff8 100644
--- a/compiler/systems/i_freertos.pas
+++ b/compiler/systems/i_freertos.pas
@@ -718,6 +718,73 @@ unit i_freertos;
             llvmdatalayout : 'e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S32';
           );
 
+       system_arm_freertos_info : tsysteminfo =
+          (
+            system       : system_arm_freertos;
+            name         : 'FreeRTOS';
+            shortname    : 'freertos';
+            flags        : [tf_needs_symbol_size,tf_files_case_sensitive,tf_requires_proper_alignment,
+                            tf_smartlink_sections,tf_init_final_units_by_calls];
+            cpu          : cpu_arm;
+            unit_env     : '';
+            extradefines : '';
+            exeext       : '';
+            defext       : '.def';
+            scriptext    : '.sh';
+            smartext     : '.sl';
+            unitext      : '.ppu';
+            unitlibext   : '.ppl';
+            asmext       : '.s';
+            objext       : '.o';
+            resext       : '.res';
+            resobjext    : '.or';
+            sharedlibext : '.so';
+            staticlibext : '.a';
+            staticlibprefix : 'libp';
+            sharedlibprefix : 'lib';
+            sharedClibext : '.so';
+            staticClibext : '.a';
+            staticClibprefix : 'lib';
+            sharedClibprefix : 'lib';
+            importlibprefix : 'libimp';
+            importlibext : '.a';
+            Cprefix      : '';
+            newline      : #10;
+            dirsep       : '/';
+            assem        : as_gas;
+            assemextern  : as_gas;
+            link         : ld_none;
+            linkextern   : ld_freertos;
+            ar           : ar_gnu_ar;
+            res          : res_none;
+            dbg          : dbg_dwarf2;
+            script       : script_unix;
+            endian       : endian_little;
+            alignment    :
+              (
+                procalign       : 4;
+                loopalign       : 4;
+                jumpalign       : 0;
+                jumpalignskipmax    : 0;
+                coalescealign   : 0;
+                coalescealignskipmax: 0;
+                constalignmin   : 0;
+                constalignmax   : 4;
+                varalignmin     : 0;
+                varalignmax     : 4;
+                localalignmin   : 4;
+                localalignmax   : 16;
+                recordalignmin  : 0;
+                recordalignmax  : 4;
+                maxCrecordalign : 4
+              );
+            first_parm_offset : 8;
+            stacksize    : 65536;
+            stackalign   : 16;
+            abi : abi_default;
+            llvmdatalayout : 'e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S32';
+          );
+
  implementation
 
 initialization
diff --git a/compiler/systems/t_embed.pas b/compiler/systems/t_embed.pas
index a4294f3d54..cdc2cc7167 100644
--- a/compiler/systems/t_embed.pas
+++ b/compiler/systems/t_embed.pas
@@ -471,6 +471,9 @@ begin
       ct_stm32f756xe,
       ct_stm32f756xg,
 
+      ct_stm32g071rb,
+      ct_nucleog071rb,
+
       { TI - 64 K Flash, 16 K SRAM Devices }
       ct_lm3s1110,
       ct_lm3s1133,
diff --git a/compiler/systems/t_freertos.pas b/compiler/systems/t_freertos.pas
index b453be6d2a..24ff1bc39f 100644
--- a/compiler/systems/t_freertos.pas
+++ b/compiler/systems/t_freertos.pas
@@ -222,479 +222,55 @@ begin
    end;
 
 {$ifdef ARM}
-  case current_settings.controllertype of
-      ct_none:
-           begin
-           end;
-      ct_lpc810m021fn8,
-      ct_lpc811m001fdh16,
-      ct_lpc812m101fdh16,
-      ct_lpc812m101fd20,
-      ct_lpc812m101fdh20,
-      ct_lpc1110fd20,
-      ct_lpc1111fdh20_002,
-      ct_lpc1111fhn33_101,
-      ct_lpc1111fhn33_102,
-      ct_lpc1111fhn33_103,
-      ct_lpc1111fhn33_201,
-      ct_lpc1111fhn33_202,
-      ct_lpc1111fhn33_203,
-      ct_lpc1112fd20_102,
-      ct_lpc1112fdh20_102,
-      ct_lpc1112fdh28_102,
-      ct_lpc1112fhn33_101,
-      ct_lpc1112fhn33_102,
-      ct_lpc1112fhn33_103,
-      ct_lpc1112fhn33_201,
-      ct_lpc1112fhn24_202,
-      ct_lpc1112fhn33_202,
-      ct_lpc1112fhn33_203,
-      ct_lpc1112fhi33_202,
-      ct_lpc1112fhi33_203,
-      ct_lpc1113fhn33_201,
-      ct_lpc1113fhn33_202,
-      ct_lpc1113fhn33_203,
-      ct_lpc1113fhn33_301,
-      ct_lpc1113fhn33_302,
-      ct_lpc1113fhn33_303,
-      ct_lpc1113bfd48_301,
-      ct_lpc1113bfd48_302,
-      ct_lpc1113bfd48_303,
-      ct_lpc1114fdh28_102,
-      ct_lpc1114fn28_102,
-      ct_lpc1114fhn33_201,
-      ct_lpc1114fhn33_202,
-      ct_lpc1114fhn33_203,
-      ct_lpc1114fhn33_301,
-      ct_lpc1114fhn33_302,
-      ct_lpc1114fhn33_303,
-      ct_lpc1114fhn33_333,
-      ct_lpc1114fhi33_302,
-      ct_lpc1114fhi33_303,
-      ct_lpc1114bfd48_301,
-      ct_lpc1114bfd48_302,
-      ct_lpc1114bfd48_303,
-      ct_lpc1114bfd48_323,
-      ct_lpc1114bfd48_333,
-      ct_lpc1115bfd48_303,
-      ct_lpc11c12fd48_301,
-      ct_lpc11c14fd48_301,
-      ct_lpc11c22fd48_301,
-      ct_lpc11c24fd48_301,
-      ct_lpc11d24fd48_301,
-      ct_lpc1224fbd48_101,
-      ct_lpc1224fbd48_121,
-      ct_lpc1224fbd64_101,
-      ct_lpc1224fbd64_121,
-      ct_lpc1225fbd48_301,
-      ct_lpc1225fbd48_321,
-      ct_lpc1225fbd64_301,
-      ct_lpc1225fbd64_321,
-      ct_lpc1226fbd48_301,
-      ct_lpc1226fbd64_301,
-      ct_lpc1227fbd48_301,
-      ct_lpc1227fbd64_301,
-      ct_lpc12d27fbd100_301,
-      ct_lpc1311fhn33,
-      ct_lpc1311fhn33_01,
-      ct_lpc1313fhn33,
-      ct_lpc1313fhn33_01,
-      ct_lpc1313fbd48,
-      ct_lpc1313fbd48_01,
-      ct_lpc1315fhn33,
-      ct_lpc1315fbd48,
-      ct_lpc1316fhn33,
-      ct_lpc1316fbd48,
-      ct_lpc1317fhn33,
-      ct_lpc1317fbd48,
-      ct_lpc1317fbd64,
-      ct_lpc1342fhn33,
-      ct_lpc1342fbd48,
-      ct_lpc1343fhn33,
-      ct_lpc1343fbd48,
-      ct_lpc1345fhn33,
-      ct_lpc1345fbd48,
-      ct_lpc1346fhn33,
-      ct_lpc1346fbd48,
-      ct_lpc1347fhn33,
-      ct_lpc1347fbd48,
-      ct_lpc1347fbd64,
-      ct_lpc2114,
-      ct_lpc2124,
-      ct_lpc2194,
-      ct_lpc1768,
-      ct_at91sam7s256,
-      ct_at91sam7se256,
-      ct_at91sam7x256,
-      ct_at91sam7xc256,
-
-      ct_stm32f030c6,
-      ct_stm32f030c8,
-      ct_stm32f030f4,
-      ct_stm32f030k6,
-      ct_stm32f030r8,
-      ct_stm32f050c4,
-      ct_stm32f050c6,
-      ct_stm32f050f4,
-      ct_stm32f050f6,
-      ct_stm32f050g4,
-      ct_stm32f050g6,
-      ct_stm32f050k4,
-      ct_stm32f050k6,
-      ct_stm32f051c4,
-      ct_stm32f051c6,
-      ct_stm32f051c8,
-      ct_stm32f051k4,
-      ct_stm32f051k6,
-      ct_stm32f051k8,
-      ct_stm32f051r4,
-      ct_stm32f051r6,
-      ct_stm32f051r8,
-
-      ct_stm32f091cc,
-      ct_stm32f091cb,
-      ct_stm32f091rc,
-      ct_stm32f091rb,
-      ct_stm32f091vc,
-      ct_stm32f091vb,
-
-      ct_stm32f100x4,
-      ct_stm32f100x6,
-      ct_stm32f100x8,
-      ct_stm32f100xB,
-      ct_stm32f100xC,
-      ct_stm32f100xD,
-      ct_stm32f100xE,
-      ct_stm32f101x4,
-      ct_stm32f101x6,
-      ct_stm32f101x8,
-      ct_stm32f101xB,
-      ct_stm32f101xC,
-      ct_stm32f101xD,
-      ct_stm32f101xE,
-      ct_stm32f101xF,
-      ct_stm32f101xG,
-      ct_stm32f102x4,
-      ct_stm32f102x6,
-      ct_stm32f102x8,
-      ct_stm32f102xB,
-      ct_stm32f103x4,
-      ct_stm32f103x6,
-      ct_stm32f103x8,
-      ct_stm32f103xB,
-      ct_stm32f103xC,
-      ct_stm32f103xD,
-      ct_stm32f103xE,
-      ct_stm32f103xF,
-      ct_stm32f103xG,
-      ct_stm32f107x8,
-      ct_stm32f107xB,
-      ct_stm32f107xC,
-      ct_stm32f105r8,
-      ct_stm32f105rb,
-      ct_stm32f105rc,
-      ct_stm32f105v8,
-      ct_stm32f105vb,
-      ct_stm32f105vc,
-      ct_stm32f107rb,
-      ct_stm32f107rc,
-      ct_stm32f107vb,
-      ct_stm32f107vc,
-      
-      ct_stm32f401cb,
-      ct_stm32f401rb,
-      ct_stm32f401vb,
-      ct_stm32f401cc,
-      ct_stm32f401rc,
-      ct_stm32f401vc,
-      ct_discoveryf401vc,
-      ct_stm32f401cd,
-      ct_stm32f401rd,
-      ct_stm32f401vd,
-      ct_stm32f401ce,
-      ct_stm32f401re,
-      ct_nucleof401re,
-      ct_stm32f401ve,
-      ct_stm32f407vg,
-      ct_discoveryf407vg,
-      ct_stm32f407ig,
-      ct_stm32f407zg,
-      ct_stm32f407ve,
-      ct_stm32f407ze,
-      ct_stm32f407ie,
-      ct_stm32f411cc,
-      ct_stm32f411rc,
-      ct_stm32f411vc,
-      ct_stm32f411ce,
-      ct_stm32f411re,
-      ct_nucleof411re,
-      ct_stm32f411ve,
-      ct_discoveryf411ve,
-      ct_stm32f429vg,
-      ct_stm32f429zg,
-      ct_stm32f429ig,
-      ct_stm32f429vi,
-      ct_stm32f429zi,
-      ct_discoveryf429zi,
-      ct_stm32f429ii,
-      ct_stm32f429ve,
-      ct_stm32f429ze,
-      ct_stm32f429ie,
-      ct_stm32f429bg,
-      ct_stm32f429bi,
-      ct_stm32f429be,
-      ct_stm32f429ng,
-      ct_stm32f429ni,
-      ct_stm32f429ne,
-      ct_stm32f446mc,
-      ct_stm32f446rc,
-      ct_stm32f446vc,
-      ct_stm32f446zc,
-      ct_stm32f446me,
-      ct_stm32f446re,
-      ct_nucleof446re,
-      ct_stm32f446ve,
-      ct_stm32f446ze,
-
-      ct_stm32f745xe,
-      ct_stm32f745xg,
-      ct_stm32f746xe,
-      ct_stm32f746xg,
-      ct_stm32f756xe,
-      ct_stm32f756xg,
-
-      { TI - 64 K Flash, 16 K SRAM Devices }
-      ct_lm3s1110,
-      ct_lm3s1133,
-      ct_lm3s1138,
-      ct_lm3s1150,
-      ct_lm3s1162,
-      ct_lm3s1165,
-      ct_lm3s1166,
-      ct_lm3s2110,
-      ct_lm3s2139,
-      ct_lm3s6100,
-      ct_lm3s6110,
-
-      { TI 128 K Flash, 32 K SRAM devices - Fury Class }
-      ct_lm3s1601,
-      ct_lm3s1608,
-      ct_lm3s1620,
-      ct_lm3s1635,
-      ct_lm3s1636,
-      ct_lm3s1637,
-      ct_lm3s1651,
-      ct_lm3s2601,
-      ct_lm3s2608,
-      ct_lm3s2620,
-      ct_lm3s2637,
-      ct_lm3s2651,
-      ct_lm3s6610,
-      ct_lm3s6611,
-      ct_lm3s6618,
-      ct_lm3s6633,
-      ct_lm3s6637,
-      ct_lm3s8630,
-
-      { TI 256 K Flase, 32 K SRAM devices - Fury Class }
-      ct_lm3s1911,
-      ct_lm3s1918,
-      ct_lm3s1937,
-      ct_lm3s1958,
-      ct_lm3s1960,
-      ct_lm3s1968,
-      ct_lm3s1969,
-      ct_lm3s2911,
-      ct_lm3s2918,
-      ct_lm3s2919,
-      ct_lm3s2939,
-      ct_lm3s2948,
-      ct_lm3s2950,
-      ct_lm3s2965,
-      ct_lm3s6911,
-      ct_lm3s6918,
-      ct_lm3s6938,
-      ct_lm3s6950,
-      ct_lm3s6952,
-      ct_lm3s6965,
-      ct_lm3s8930,
-      ct_lm3s8933,
-      ct_lm3s8938,
-      ct_lm3s8962,
-      ct_lm3s8970,
-      ct_lm3s8971,
-
-      { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
-      ct_lm3s5951,
-      ct_lm3s5956,
-      ct_lm3s1b21,
-      ct_lm3s2b93,
-      ct_lm3s5b91,
-      ct_lm3s9b81,
-      ct_lm3s9b90,
-      ct_lm3s9b92,
-      ct_lm3s9b95,
-      ct_lm3s9b96,
-      
-      ct_lm3s5d51,
-      
-      { TI - Stellaris something }
-      ct_lm4f120h5,
-      
-      { Infineon }
-      ct_xmc4500x1024,
-      ct_xmc4500x768,
-      ct_xmc4502x768,
-      ct_xmc4504x512,
-
-      { Allwinner }
-      ct_allwinner_a20,
-
-      { Freescale }
-      ct_mk20dx128vfm5,
-      ct_mk20dx128vft5,
-      ct_mk20dx128vlf5,
-      ct_mk20dx128vlh5,
-      ct_teensy30,
-      ct_mk20dx128vmp5,
-
-      ct_mk20dx32vfm5,
-      ct_mk20dx32vft5,
-      ct_mk20dx32vlf5,
-      ct_mk20dx32vlh5,
-      ct_mk20dx32vmp5,
-
-      ct_mk20dx64vfm5,
-      ct_mk20dx64vft5,
-      ct_mk20dx64vlf5,
-      ct_mk20dx64vlh5,
-      ct_mk20dx64vmp5,
-
-      ct_mk20dx128vlh7,
-      ct_mk20dx128vlk7,
-      ct_mk20dx128vll7,
-      ct_mk20dx128vmc7,
-
-      ct_mk20dx256vlh7,
-      ct_mk20dx256vlk7,
-      ct_mk20dx256vll7,
-      ct_mk20dx256vmc7,
-      ct_teensy31,
-      ct_teensy32,
-
-      ct_mk20dx64vlh7,
-      ct_mk20dx64vlk7,
-      ct_mk20dx64vmc7,
-
-      ct_mk22fn512cap12,
-      ct_mk22fn512cbp12,
-      ct_mk22fn512vdc12,
-      ct_mk22fn512vlh12,
-      ct_mk22fn512vll12,
-      ct_mk22fn512vmp12,
-      ct_freedom_k22f,
- 
-      { Atmel }
-      ct_sam3x8e,
-      ct_arduino_due,
-      ct_flip_n_click,
-      
-      { Nordic Semiconductor }
-      ct_nrf51422_xxaa,
-      ct_nrf51422_xxab,
-      ct_nrf51422_xxac,
-      ct_nrf51822_xxaa,
-      ct_nrf51822_xxab,
-      ct_nrf51822_xxac,
-      ct_nrf52832_xxaa,
-      ct_nrf52840_xxaa,
-      
-      ct_sc32442b,
-
-      { Raspberry Pi 2 }
-      ct_raspi2,
-
-      ct_thumb2bare:
-        begin
-         with embedded_controllers[current_settings.controllertype] do
-          with linkres do
-            begin
-              if (embedded_controllers[current_settings.controllertype].controllerunitstr='MK20D5')
-              or (embedded_controllers[current_settings.controllertype].controllerunitstr='MK20D7')
-              or (embedded_controllers[current_settings.controllertype].controllerunitstr='MK22F51212')
-              or (embedded_controllers[current_settings.controllertype].controllerunitstr='MK64F12') then
-                Add('ENTRY(_LOWLEVELSTART)')
-              else
-                Add('ENTRY(_START)');
-              Add('MEMORY');
-              Add('{');
-              if flashsize<>0 then
-                begin
-                  LinkStr := '    flash : ORIGIN = 0x' + IntToHex(flashbase,8)
-                    + ', LENGTH = 0x' + IntToHex(flashsize,8);
-                  Add(LinkStr);
-                end;
-
-              LinkStr := '    ram : ORIGIN = 0x' + IntToHex(srambase,8)
-              	+ ', LENGTH = 0x' + IntToHex(sramsize,8);
-              Add(LinkStr);
-
-              Add('}');
-              Add('_stack_top = 0x' + IntToHex(sramsize+srambase,8) + ';');
-    
-              // Add Checksum Calculation for LPC Controllers so that the bootloader starts the uploaded binary 
-              writeln(controllerunitstr);
-              if (controllerunitstr = 'LPC8xx') or (controllerunitstr = 'LPC11XX') or (controllerunitstr = 'LPC122X') then
-                Add('Startup_Checksum = 0 - (_stack_top + _START + 1 + NonMaskableInt_interrupt + 1 + Hardfault_interrupt + 1);');
-              if (controllerunitstr = 'LPC13XX') then
-                Add('Startup_Checksum = 0 - (_stack_top + _START + 1 + NonMaskableInt_interrupt + 1 + MemoryManagement_interrupt + 1 + BusFault_interrupt + 1 + UsageFault_interrupt + 1);');
-            end;
-        end
-    else
-      if not (cs_link_nolink in current_settings.globalswitches) then
-      	 internalerror(200902011);
-  end;
+  with embedded_controllers[current_settings.controllertype] do
+    with linkres do
+      begin
+        Add('ENTRY(_START)');
+        Add('MEMORY');
+        Add('{');
+        if flashsize<>0 then
+          begin
+            LinkStr := '    flash : ORIGIN = 0x' + IntToHex(flashbase,8)
+              + ', LENGTH = 0x' + IntToHex(flashsize,8);
+            Add(LinkStr);
+          end;
 
-  with linkres do
-    begin
-      Add('SECTIONS');
-      Add('{');
-      Add('     .text :');
-      Add('    {');
-      Add('    _text_start = .;');
-      Add('    KEEP(*(.init .init.*))');
-      if (embedded_controllers[current_settings.controllertype].controllerunitstr='MK20D5')
-         or (embedded_controllers[current_settings.controllertype].controllerunitstr='MK20D7')
-         or (embedded_controllers[current_settings.controllertype].controllerunitstr='MK22F51212')
-         or (embedded_controllers[current_settings.controllertype].controllerunitstr='MK64F12') then
-        begin
-          Add('    . = 0x400;');
-          Add('    KEEP(*(.flash_config *.flash_config.*))');
-        end;
-      Add('    *(.text .text.*)');
-      Add('    *(.strings)');
-      Add('    *(.rodata .rodata.*)');
-      Add('    *(.comment)');
-      Add('    . = ALIGN(4);');
-      Add('    _etext = .;');
-      if embedded_controllers[current_settings.controllertype].flashsize<>0 then
-        begin
-          Add('    } >flash');
-          Add('    .note.gnu.build-id : { *(.note.gnu.build-id) } >flash ');
-        end
-      else
-        begin
-          Add('    } >ram');
-          Add('    .note.gnu.build-id : { *(.note.gnu.build-id) } >ram ');
-        end;
+        LinkStr := '    ram : ORIGIN = 0x' + IntToHex(srambase,8)
+          + ', LENGTH = 0x' + IntToHex(sramsize,8);
+        Add(LinkStr);
+
+        Add('}');
+        Add('_stack_top = 0x' + IntToHex(sramsize+srambase,8) + ';');
+        Add('SECTIONS');
+        Add('{');
+        Add('    .text :');
+        Add('    {');
+        Add('    _text_start = .;');
+        Add('    KEEP(*(.init .init.*))');
+        Add('    *(.text .text.*)');
+        Add('    *(.strings)');
+        Add('    *(.rodata .rodata.*)');
+        Add('    *(.comment)');
+        Add('    . = ALIGN(4);');
+        Add('    _etext = .;');
+        if flashsize<>0 then
+          begin
+            Add('    } >flash');
+            Add('    .note.gnu.build-id : { *(.note.gnu.build-id) } >flash ');
+          end
+        else
+          begin
+            Add('    } >ram');
+            Add('    .note.gnu.build-id : { *(.note.gnu.build-id) } >ram ');
+          end;
 
-      Add('    .data :');
-      Add('    {');
-      Add('    _data = .;');
-      Add('    *(.data .data.*)');
-      Add('    KEEP (*(.fpc .fpc.n_version .fpc.n_links))');
-      Add('    _edata = .;');
-      if embedded_controllers[current_settings.controllertype].flashsize<>0 then
+        Add('    .data :');
+        Add('    {');
+        Add('    _data = .;');
+        Add('    *(.data .data.*)');
+        Add('    KEEP (*(.fpc .fpc.n_version .fpc.n_links))');
+        Add('    _edata = .;');
+      if flashsize<>0 then
         begin
           Add('    } >ram AT >flash');
         end
@@ -708,8 +284,8 @@ begin
       Add('    *(.bss .bss.*)');
       Add('    *(COMMON)');
       Add('    } >ram');
-      Add('. = ALIGN(4);');
-      Add('_bss_end = . ;');
+      Add('    . = ALIGN(4);');
+      Add('    _bss_end = . ;');
       Add('}');
       Add('_end = .;');
     end;
@@ -1609,8 +1185,9 @@ begin
     Replace(cmdstr,'$GCSECTIONS',GCSectionsStr);
     Replace(cmdstr,'$DYNLINK',DynLinkStr);
    end;
-  if success and not(cs_link_nolink in current_settings.globalswitches) then
-    success:=DoExec(FindUtil(utilsprefix+BinStr),cmdstr,true,false);
+  //write(FindUtil(utilsprefix+BinStr+' '));
+  //writeln(cmdstr);
+  success:=DoExec(FindUtil(utilsprefix+BinStr),cmdstr,true,false);
 
 { Remove ReponseFile }
   if success and not(cs_link_nolink in current_settings.globalswitches) then
@@ -1804,8 +1381,8 @@ function TlinkerFreeRTOS.postprocessexecutable(const fn : string;isdll:boolean):
 
 initialization
 {$ifdef arm}
-  RegisterLinker(ld_freertos,TLinkerEmbedded);
-  RegisterTarget(system_arm_embedded_info);
+  RegisterLinker(ld_freertos,TlinkerFreeRTOS);
+  RegisterTarget(system_arm_freertos_info);
 {$endif arm}
 
 {$ifdef avr}
diff --git a/compiler/utils/ppuutils/ppudump.pp b/compiler/utils/ppuutils/ppudump.pp
index c401880c2d..470aed905b 100644
--- a/compiler/utils/ppuutils/ppudump.pp
+++ b/compiler/utils/ppuutils/ppudump.pp
@@ -224,6 +224,7 @@ const
   { 103 } 'Embedded-Xtensa',
   { 104 } 'FreeRTos-Xtensa',
   { 105 } 'Linux-Xtensa'
+  { 106 } 'FreeRTos-arm'
   );
 
 const
diff --git a/rtl/freertos/Makefile.fpc b/rtl/freertos/Makefile.fpc
index d8e429cc63..12efa1ba60 100644
--- a/rtl/freertos/Makefile.fpc
+++ b/rtl/freertos/Makefile.fpc
@@ -73,11 +73,11 @@ CPU_SPECIFIC_COMMON_UNITS=
 ifeq ($(ARCH),arm)
 CPU_SPECIFIC_COMMON_UNITS=sysutils math classes fgl macpas typinfo types rtlconsts getopts lineinfo
 ifeq ($(SUBARCH),armv7m)
-CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn stm32f10x_cl lpc13xx lpc1768 lm4f120 sam3x8e xmc4500 cortexm3 cortexm4 # thumb2_bare
+CPU_UNITS=stm32f103xe cortexm3 cortexm4 # thumb2_bare
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),armv7em)
-CPU_UNITS=lm4f120 xmc4500 mk20d5 mk20d7 mk22f51212 mk64f12 stm32f401xx stm32f407xx stm32f411xe stm32f429xx stm32f446xx stm32f745 stm32f746 stm32f756 nrf52 cortexm3 cortexm4 cortexm7 # thumb2_bare
+CPU_UNITS=stm32f401xe cortexm3 cortexm4 cortexm7 # thumb2_bare
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),armv4t)
@@ -89,7 +89,7 @@ CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),armv6m)
-CPU_UNITS=lpc8xx lpc11xx lpc122x stm32f0xx nrf51 cortexm0
+CPU_UNITS=stm32g071xx cortexm0
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),armv7a)
diff --git a/rtl/freertos/arm/cortexm0.pp b/rtl/freertos/arm/cortexm0.pp
new file mode 100644
index 0000000000..dfa5a44f51
--- /dev/null
+++ b/rtl/freertos/arm/cortexm0.pp
@@ -0,0 +1,78 @@
+{
+ System register definitions and utility code for Cortex-M0
+ Created by Jeppe Johansen 2012 - jeppe@j-software.dk
+ Modified for M0 by Michael Ring 2013 - mail@michael-ring.org
+}
+unit cortexm0;
+
+interface
+
+{$PACKRECORDS 2}
+const
+ SCS_BASE   = $E000E000;
+ SysTick_BASE = SCS_BASE+$0010;
+ NVIC_BASE = SCS_BASE+$0100;
+ SCB_BASE = SCS_BASE+$0D00;
+
+ DWT_BASE   = $E0001000;
+ FP_BASE    = $E0002000;
+ ITM_BASE   = $E0000000;
+ TPIU_BASE  = $E0040000;
+ ETM_BASE   = $E0041000;
+
+type
+
+ TNVICRegisters = record
+   ISER : dword;
+   RESERVED0 : array[0..30] of dword;
+   ICER : dword;
+   RSERVED1 : array[0..30] of dword;
+   ISPR : dword;
+   RESERVED2 : array[0..30] of dword;
+   ICPR : dword;
+   RESERVED3 : array[0..30] of dword;
+   RESERVED4 : array[0..63] of dword;
+   IPR : array[0..7] of dword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  RESERVED0,
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: dword;                       {!< Configuration Control Register                           }
+  RESERVED1 : dword;
+  SHP: array[0..1] of dword;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: dword;
+ end;
+
+ TCoreDebugRegisters = record
+  DHCSR,
+  DCRSR,
+  DCRDR,
+  DEMCR: longword;
+ end;
+
+
+var
+ // System Control
+ InterruptControlType: longword     absolute (SCS_BASE+$0004);
+ SCB: TSCBRegisters                 absolute (SCS_BASE+$0D00);
+ SysTick: TSysTickRegisters         absolute (SCS_BASE+$0010);
+ NVIC: TNVICRegisters               absolute (SCS_BASE+$0100);
+ SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
+
+ // Core Debug
+ CoreDebug: TCoreDebugRegisters     absolute (SCS_BASE+$0DF0);
+
+
+implementation
+
+end.
diff --git a/rtl/freertos/arm/cortexm0_start.inc b/rtl/freertos/arm/cortexm0_start.inc
new file mode 100644
index 0000000000..c5c84c63de
--- /dev/null
+++ b/rtl/freertos/arm/cortexm0_start.inc
@@ -0,0 +1,75 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _text_start: record end; external name '_text_start';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+   b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+  ldr r1,.L_etext
+  ldr r2,.L_data
+  ldr r3,.L_edata
+  mov r4,#4
+.Lcopyloop:
+//  cmp r2,r3
+//  ittt ls
+//  ldrls r0,[r1],#4
+//  strls r0,[r2],#4
+//  bls .Lcopyloop
+    ldr r0,[r1]
+    str r0,[r2]
+    add r1,r1,r4
+    add r2,r2,r4
+    cmp r2,r3
+    bls .Lcopyloop
+  // clear onboard ram
+  ldr r1,.L_bss_start
+  ldr r2,.L_bss_end
+  mov r0,#0
+.Lzeroloop:
+  //cmp r1,r2
+  //itt ls
+  //strls r0,[r1],#4
+  //bls .Lzeroloop
+  str r0,[r1]
+  add r1,r1,r4
+  cmp r1,r2
+  bls .Lzeroloop
+
+{$ifdef REMAP_VECTTAB}
+  ldr r0, .Lvtor
+  ldr r1, .Ltext_start
+  str r1, [r0]
+{$endif REMAP_VECTTAB}
+
+  bl PASCALMAIN
+  b HaltProc
+
+.L_bss_start:
+  .long _bss_start
+.L_bss_end:
+  .long _bss_end
+.L_etext:
+  .long _etext
+.L_data:
+  .long _data
+.L_edata:
+  .long _edata
+{$ifdef REMAP_VECTTAB}
+.Lvtor:
+  .long 0xE000ED08
+.Ltext_start:
+  .long _text_start
+{$endif REMAP_VECTTAB}
+end;
diff --git a/rtl/freertos/arm/cortexm3.pp b/rtl/freertos/arm/cortexm3.pp
new file mode 100644
index 0000000000..9fa76d4cfa
--- /dev/null
+++ b/rtl/freertos/arm/cortexm3.pp
@@ -0,0 +1,189 @@
+{
+ System register definitions and utility code for Cortex-M3
+
+ Created by Jeppe Johansen 2012 - jeppe@j-software.dk
+}
+unit cortexm3;
+
+interface
+
+{$PACKRECORDS 2}
+const
+ SCS_BASE   = $E000E000;
+ DWT_BASE   = $E0001000;
+ FP_BASE    = $E0002000;
+ ITM_BASE   = $E0000000;
+ TPIU_BASE  = $E0040000;
+ ETM_BASE   = $E0041000;
+
+type
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of byte;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+ TIDRegisters = record
+  PID4_7: array[0..3] of longword;
+  PID0_3: array[0..3] of longword;
+  CID: array[0..3] of longword;
+ end;
+
+ TCoreDebugRegisters = record
+  DHCSR,
+  DCRSR,
+  DCRDR,
+  DEMCR: longword;
+ end;
+
+ TFPRegisters = record
+  Ctrl,
+  Remap: longword;
+  Comp: array[0..7] of longword;
+  res: array[0..987] of longword;
+  ID: TIDRegisters;
+ end;
+
+ TDWTEntry = record
+  Comp,
+  Mask,
+  Func,
+  res: longword;
+ end;
+
+ TDWTRegisters = record
+  Ctrl,
+  CycCnt,
+  CPICnt,
+  ExcCnt,
+  SleepCnt,
+  LSUCnt,
+  FoldCnt,
+  PCSR: longword;
+  Entries: array[0..3] of TDWTEntry;
+ end;
+
+ TITMRegisters = record
+  Stimulus: array[0..31] of longword;
+   res0: array[0..($E00-$7C-4)-1] of byte;
+  TraceEnable: longword;
+   res1: array[0..($E40-$E00-4)-1] of byte;
+  TracePrivilege: longword;
+   res2: array[0..($E80-$E40-4)-1] of byte;
+  TraceControl: longword;
+   res3: array[0..($EF8-$E80-4)-1] of byte;
+  IntegrationWrite,
+  IntegrationRead,
+  IntegrationModeCtrl: longword;
+   res4: array[0..($FB0-$F00-4)-1] of byte;
+  LockAccess,
+  LockStatus: longword;
+   res5: array[0..($FD0-$FB4-4)-1] of byte;
+  ID: TIDRegisters;
+ end;
+
+ TTPIURegisters = record
+  SupportedSyncPortSizes,
+  CurrentSyncPortSize: longword;
+   res0: array[0..($10-$04-4)-1] of byte;
+  AsyncColckPrescaler: longword;
+   res1: array[0..($F0-$10-4)-1] of byte;
+  SelectedPinProtocol: longword;
+   res2: array[0..($100-$F0-4)-1] of byte;
+  TriggerControl: array[0..2] of longword;
+   res3: array[0..($200-$108-4)-1] of byte;
+  TestPattern: array[0..2] of longword;
+   res4: array[0..($300-$208-4)-1] of byte;
+  FormatFlushStatus,
+  FormatControl,
+  FormatSyncCounter: longword;
+   res5: array[0..($EF0-$308-4)-1] of byte;
+  ITATBCTR2: longword;
+   res6: longword;
+  ITATBCTR0: longword;
+ end;
+
+var
+ // System Control
+ InterruptControlType: longword     absolute (SCS_BASE+$0004);
+ SCB: TSCBRegisters                 absolute (SCS_BASE+$0D00);
+ SysTick: TSysTickRegisters         absolute (SCS_BASE+$0010);
+ NVIC: TNVICRegisters               absolute (SCS_BASE+$0100);
+ SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
+ SCBID: TIDRegisters                absolute (SCS_BASE+$EFD0);
+
+ // Core Debug
+ CoreDebug: TCoreDebugRegisters     absolute (SCS_BASE+$0DF0);
+
+ // Flash Patch
+ FP: TFPRegisters                   absolute FP_BASE;
+
+ DWT: TDWTRegisters                 absolute DWT_BASE;
+
+ ITM: TITMRegisters                 absolute ITM_BASE;
+
+ TPIU: TTPIURegisters               absolute TPIU_BASE;
+
+type
+ TITM_Port = 0..31;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword); inline;
+
+implementation
+
+const
+ CoreDebug_DEMCR_TRCENA = $01000000;
+ ITM_TCR_ITMENA   = $00000001;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword);
+begin
+   if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and
+      ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and
+      ((ITM.TraceEnable and (1 shl Port)) <> 0) then
+   begin
+      while ITM.Stimulus[Port] = 0 do;
+      ITM.Stimulus[Port] := Data;
+   end;
+end;
+
+end.
diff --git a/rtl/freertos/arm/cortexm3_start.inc b/rtl/freertos/arm/cortexm3_start.inc
new file mode 100644
index 0000000000..82202b1565
--- /dev/null
+++ b/rtl/freertos/arm/cortexm3_start.inc
@@ -0,0 +1,65 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _text_start: record end; external name '_text_start';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+   b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+  ldr r1,.L_etext
+  ldr r2,.L_data
+  ldr r3,.L_edata
+.Lcopyloop:
+  cmp r2,r3
+  ittt ls
+  ldrls r0,[r1],#4
+  strls r0,[r2],#4
+  bls .Lcopyloop
+
+  // clear onboard ram
+  ldr r1,.L_bss_start
+  ldr r2,.L_bss_end
+  mov r0,#0
+.Lzeroloop:
+  cmp r1,r2
+  itt ls
+  strls r0,[r1],#4
+  bls .Lzeroloop
+
+{$ifdef REMAP_VECTTAB}
+  ldr r0, .Lvtor
+  ldr r1, .Ltext_start
+  str r1, [r0]
+{$endif REMAP_VECTTAB}
+
+  bl PASCALMAIN
+  b HaltProc
+
+.L_bss_start:
+  .long _bss_start
+.L_bss_end:
+  .long _bss_end
+.L_etext:
+  .long _etext
+.L_data:
+  .long _data
+.L_edata:
+  .long _edata
+{$ifdef REMAP_VECTTAB}
+.Lvtor:
+  .long 0xE000ED08
+.Ltext_start:
+  .long _text_start
+{$endif REMAP_VECTTAB}
+end;
\ No newline at end of file
diff --git a/rtl/freertos/arm/cortexm4.pp b/rtl/freertos/arm/cortexm4.pp
new file mode 100644
index 0000000000..aa4685b249
--- /dev/null
+++ b/rtl/freertos/arm/cortexm4.pp
@@ -0,0 +1,189 @@
+{
+ System register definitions and utility code for Cortex-M4
+
+ Created by Jeppe Johansen 2012 - jeppe@j-software.dk
+}
+unit cortexm4;
+
+interface
+
+{$PACKRECORDS 2}
+const
+ SCS_BASE   = $E000E000;
+ DWT_BASE   = $E0001000;
+ FP_BASE    = $E0002000;
+ ITM_BASE   = $E0000000;
+ TPIU_BASE  = $E0040000;
+ ETM_BASE   = $E0041000;
+
+type
+
+ TNVICRegisters = record
+  ISER: array[0..7] of longword;
+   reserved0: array[0..23] of longword;
+  ICER: array[0..7] of longword;
+   reserved1: array[0..23] of longword;
+  ISPR: array[0..7] of longword;
+   reserved2: array[0..23] of longword;
+  ICPR: array[0..7] of longword;
+   reserved3: array[0..23] of longword;
+  IABR: array[0..7] of longword;
+   reserved4: array[0..55] of longword;
+  IP: array[0..239] of byte;
+   reserved5: array[0..643] of longword;
+  STIR: longword;
+ end;
+
+ TSCBRegisters = record
+  CPUID,                            {!< CPU ID Base Register                                     }
+  ICSR,                             {!< Interrupt Control State Register                         }
+  VTOR,                             {!< Vector Table Offset Register                             }
+  AIRCR,                            {!< Application Interrupt / Reset Control Register           }
+  SCR,                              {!< System Control Register                                  }
+  CCR: longword;                    {!< Configuration Control Register                           }
+  SHP: array[0..11] of byte;        {!< System Handlers Priority Registers (4-7, 8-11, 12-15)    }
+  SHCSR,                            {!< System Handler Control and State Register                }
+  CFSR,                             {!< Configurable Fault Status Register                       }
+  HFSR,                             {!< Hard Fault Status Register                               }
+  DFSR,                             {!< Debug Fault Status Register                              }
+  MMFAR,                            {!< Mem Manage Address Register                              }
+  BFAR,                             {!< Bus Fault Address Register                               }
+  AFSR: longword;                   {!< Auxiliary Fault Status Register                          }
+  PFR: array[0..1] of longword;     {!< Processor Feature Register                               }
+  DFR,                              {!< Debug Feature Register                                   }
+  ADR: longword;                    {!< Auxiliary Feature Register                               }
+  MMFR: array[0..3] of longword;    {!< Memory Model Feature Register                            }
+  ISAR: array[0..4] of longword;    {!< ISA Feature Register                                     }
+ end;
+
+ TSysTickRegisters = record
+  Ctrl,
+  Load,
+  Val,
+  Calib: longword;
+ end;
+
+ TIDRegisters = record
+  PID4_7: array[0..3] of longword;
+  PID0_3: array[0..3] of longword;
+  CID: array[0..3] of longword;
+ end;
+
+ TCoreDebugRegisters = record
+  DHCSR,
+  DCRSR,
+  DCRDR,
+  DEMCR: longword;
+ end;
+
+ TFPRegisters = record
+  Ctrl,
+  Remap: longword;
+  Comp: array[0..7] of longword;
+  res: array[0..987] of longword;
+  ID: TIDRegisters;
+ end;
+
+ TDWTEntry = record
+  Comp,
+  Mask,
+  Func,
+  res: longword;
+ end;
+
+ TDWTRegisters = record
+  Ctrl,
+  CycCnt,
+  CPICnt,
+  ExcCnt,
+  SleepCnt,
+  LSUCnt,
+  FoldCnt,
+  PCSR: longword;
+  Entries: array[0..3] of TDWTEntry;
+ end;
+
+ TITMRegisters = record
+  Stimulus: array[0..31] of longword;
+   res0: array[0..($E00-$7C-4)-1] of byte;
+  TraceEnable: longword;
+   res1: array[0..($E40-$E00-4)-1] of byte;
+  TracePrivilege: longword;
+   res2: array[0..($E80-$E40-4)-1] of byte;
+  TraceControl: longword;
+   res3: array[0..($EF8-$E80-4)-1] of byte;
+  IntegrationWrite,
+  IntegrationRead,
+  IntegrationModeCtrl: longword;
+   res4: array[0..($FB0-$F00-4)-1] of byte;
+  LockAccess,
+  LockStatus: longword;
+   res5: array[0..($FD0-$FB4-4)-1] of byte;
+  ID: TIDRegisters;
+ end;
+
+ TTPIURegisters = record
+  SupportedSyncPortSizes,
+  CurrentSyncPortSize: longword;
+   res0: array[0..($10-$04-4)-1] of byte;
+  AsyncColckPrescaler: longword;
+   res1: array[0..($F0-$10-4)-1] of byte;
+  SelectedPinProtocol: longword;
+   res2: array[0..($100-$F0-4)-1] of byte;
+  TriggerControl: array[0..2] of longword;
+   res3: array[0..($200-$108-4)-1] of byte;
+  TestPattern: array[0..2] of longword;
+   res4: array[0..($300-$208-4)-1] of byte;
+  FormatFlushStatus,
+  FormatControl,
+  FormatSyncCounter: longword;
+   res5: array[0..($EF0-$308-4)-1] of byte;
+  ITATBCTR2: longword;
+   res6: longword;
+  ITATBCTR0: longword;
+ end;
+
+var
+ // System Control
+ InterruptControlType: longword     absolute (SCS_BASE+$0004);
+ SCB: TSCBRegisters                 absolute (SCS_BASE+$0D00);
+ SysTick: TSysTickRegisters         absolute (SCS_BASE+$0010);
+ NVIC: TNVICRegisters               absolute (SCS_BASE+$0100);
+ SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
+ SCBID: TIDRegisters                absolute (SCS_BASE+$EFD0);
+
+ // Core Debug
+ CoreDebug: TCoreDebugRegisters     absolute (SCS_BASE+$0DF0);
+
+ // Flash Patch
+ FP: TFPRegisters                   absolute FP_BASE;
+
+ DWT: TDWTRegisters                 absolute DWT_BASE;
+
+ ITM: TITMRegisters                 absolute ITM_BASE;
+
+ TPIU: TTPIURegisters               absolute TPIU_BASE;
+
+type
+ TITM_Port = 0..31;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword); inline;
+
+implementation
+
+const
+ CoreDebug_DEMCR_TRCENA = $01000000;
+ ITM_TCR_ITMENA   = $00000001;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword);
+begin
+   if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and
+      ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and
+      ((ITM.TraceEnable and (1 shl Port)) <> 0) then
+   begin
+      while ITM.Stimulus[Port] = 0 do;
+      ITM.Stimulus[Port] := Data;
+   end;
+end;
+
+end.
diff --git a/rtl/freertos/arm/cortexm4f_start.inc b/rtl/freertos/arm/cortexm4f_start.inc
new file mode 100644
index 0000000000..82202b1565
--- /dev/null
+++ b/rtl/freertos/arm/cortexm4f_start.inc
@@ -0,0 +1,65 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _text_start: record end; external name '_text_start';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+   b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+  ldr r1,.L_etext
+  ldr r2,.L_data
+  ldr r3,.L_edata
+.Lcopyloop:
+  cmp r2,r3
+  ittt ls
+  ldrls r0,[r1],#4
+  strls r0,[r2],#4
+  bls .Lcopyloop
+
+  // clear onboard ram
+  ldr r1,.L_bss_start
+  ldr r2,.L_bss_end
+  mov r0,#0
+.Lzeroloop:
+  cmp r1,r2
+  itt ls
+  strls r0,[r1],#4
+  bls .Lzeroloop
+
+{$ifdef REMAP_VECTTAB}
+  ldr r0, .Lvtor
+  ldr r1, .Ltext_start
+  str r1, [r0]
+{$endif REMAP_VECTTAB}
+
+  bl PASCALMAIN
+  b HaltProc
+
+.L_bss_start:
+  .long _bss_start
+.L_bss_end:
+  .long _bss_end
+.L_etext:
+  .long _etext
+.L_data:
+  .long _data
+.L_edata:
+  .long _edata
+{$ifdef REMAP_VECTTAB}
+.Lvtor:
+  .long 0xE000ED08
+.Ltext_start:
+  .long _text_start
+{$endif REMAP_VECTTAB}
+end;
\ No newline at end of file
diff --git a/rtl/freertos/arm/cortexm7.pp b/rtl/freertos/arm/cortexm7.pp
new file mode 100644
index 0000000000..db3c789587
--- /dev/null
+++ b/rtl/freertos/arm/cortexm7.pp
@@ -0,0 +1,256 @@
+{
+ System register definitions and utility code for Cortex-M7
+
+ Created by Jeppe Johansen 2015 - jeppe@j-software.dk
+}
+unit cortexm7;
+
+interface
+
+{$PACKRECORDS C}
+type
+  NVIC_Type = record
+    ISER: array [0..7] of longword;  (*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register            *)
+    RESERVED0: array [0..23] of longword;
+    ICER: array [0..7] of longword;  (*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          *)
+    RSERVED1: array [0..23] of longword;
+    ISPR: array [0..7] of longword;  (*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           *)
+    RESERVED2: array [0..23] of longword;
+    ICPR: array [0..7] of longword;  (*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         *)
+    RESERVED3: array [0..23] of longword;
+    IABR: array [0..7] of longword;  (*!< Offset: 0x200 (R/W)  Interrupt Active bit Register            *)
+    RESERVED4: array [0..55] of longword;
+    IP: array [0..239] of byte;  (*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide)  *)
+    RESERVED5: array [0..643] of longword;
+    STIR: longword;  (*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register      *)
+  end;
+
+  SCB_Type = record
+    CPUID: longword;   (*!< Offset: 0x000 (R/ )  CPUID Base Register                                    *)
+    ICSR: longword;    (*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                   *)
+    VTOR: longword;    (*!< Offset: 0x008 (R/W)  Vector Table Offset Register                           *)
+    AIRCR: longword;   (*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register       *)
+    SCR: longword;     (*!< Offset: 0x010 (R/W)  System Control Register                                *)
+    CCR: longword;     (*!< Offset: 0x014 (R/W)  Configuration Control Register                         *)
+    SHPR: array [0..11] of byte;  (*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15)  *)
+    SHCSR: longword;   (*!< Offset: 0x024 (R/W)  System Handler Control and State Register              *)
+    CFSR: longword;    (*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                     *)
+    HFSR: longword;    (*!< Offset: 0x02C (R/W)  HardFault Status Register                              *)
+    DFSR: longword;    (*!< Offset: 0x030 (R/W)  Debug Fault Status Register                            *)
+    MMFAR: longword;   (*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                       *)
+    BFAR: longword;    (*!< Offset: 0x038 (R/W)  BusFault Address Register                              *)
+    AFSR: longword;    (*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                        *)
+    ID_PFR: array [0..1] of longword;  (*!< Offset: 0x040 (R/ )  Processor Feature Register                             *)
+    ID_DFR: longword;  (*!< Offset: 0x048 (R/ )  Debug Feature Register                                 *)
+    ID_AFR: longword;  (*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                             *)
+    ID_MFR: array [0..3] of longword;  (*!< Offset: 0x050 (R/ )  Memory Model Feature Register                          *)
+    ID_ISAR: array [0..4] of longword;  (*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                    *)
+    RESERVED0: array [0..0] of longword;
+    CLIDR: longword;   (*!< Offset: 0x078 (R/ )  Cache Level ID register                                *)
+    CTR: longword;     (*!< Offset: 0x07C (R/ )  Cache Type register                                    *)
+    CCSIDR: longword;  (*!< Offset: 0x080 (R/ )  Cache Size ID Register                                 *)
+    CSSELR: longword;  (*!< Offset: 0x084 (R/W)  Cache Size Selection Register                          *)
+    CPACR: longword;   (*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                    *)
+    RESERVED3: array [0..92] of longword;
+    STIR: longword;  (*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                  *)
+    RESERVED4: array [0..14] of longword;
+    MVFR0: longword;  (*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                       *)
+    MVFR1: longword;  (*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                       *)
+    MVFR2: longword;  (*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                       *)
+    RESERVED5: array [0..0] of longword;
+    ICIALLU: longword;  (*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                          *)
+    RESERVED6: array [0..0] of longword;
+    ICIMVAU: longword;   (*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                       *)
+    DCIMVAC: longword;   (*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                       *)
+    DCISW: longword;     (*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                          *)
+    DCCMVAU: longword;   (*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                            *)
+    DCCMVAC: longword;   (*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                            *)
+    DCCSW: longword;     (*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                               *)
+    DCCIMVAC: longword;  (*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC             *)
+    DCCISW: longword;    (*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way                *)
+    RESERVED7: array [0..5] of longword;
+    ITCMCR: longword;  (*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register    *)
+    DTCMCR: longword;  (*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers          *)
+    AHBPCR: longword;  (*!< Offset: 0x298 (R/W)  AHBP Control Register                                  *)
+    CACR: longword;    (*!< Offset: 0x29C (R/W)  L1 Cache Control Register                              *)
+    AHBSCR: longword;  (*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                             *)
+    RESERVED8: array [0..0] of longword;
+    ABFSR: longword;  (*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                    *)
+  end;
+
+  SCnSCB_Type = record
+    RESERVED0: array [0..0] of longword;
+    ICTR: longword;   (*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register       *)
+    ACTLR: longword;  (*!< Offset: 0x008 (R/W)  Auxiliary Control Register               *)
+  end;
+
+  SysTick_Type = record
+    CTRL: longword;   (*!< Offset: 0x000 (R/W)  SysTick Control and Status Register  *)
+    LOAD: longword;   (*!< Offset: 0x004 (R/W)  SysTick Reload Value Register        *)
+    VAL: longword;    (*!< Offset: 0x008 (R/W)  SysTick Current Value Register       *)
+    CALIB: longword;  (*!< Offset: 0x00C (R/ )  SysTick Calibration Register         *)
+  end;
+
+  ITM_Type = record
+    PORT: array [0..31] of record
+      case integer of
+        0: (u8: byte;);       (*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                    *)
+        1: (u16: word;);      (*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                   *)
+        2: (u32: longword;);  (*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                   *)
+    end;
+    (*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers                *)
+    RESERVED0: array [0..863] of longword;
+    TER: longword;  (*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                  *)
+    RESERVED1: array [0..14] of longword;
+    TPR: longword;  (*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register               *)
+    RESERVED2: array [0..14] of longword;
+    TCR: longword;  (*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                 *)
+    RESERVED3: array [0..28] of longword;
+    IWR: longword;   (*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register             *)
+    IRR: longword;   (*!< Offset: 0xEFC (R/ )  ITM Integration Read Register              *)
+    IMCR: longword;  (*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register      *)
+    RESERVED4: array [0..42] of longword;
+    LAR: longword;  (*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                   *)
+    LSR: longword;  (*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                   *)
+    RESERVED5: array [0..5] of longword;
+    PID4: longword;  (*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4  *)
+    PID5: longword;  (*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5  *)
+    PID6: longword;  (*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6  *)
+    PID7: longword;  (*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7  *)
+    PID0: longword;  (*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0  *)
+    PID1: longword;  (*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1  *)
+    PID2: longword;  (*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2  *)
+    PID3: longword;  (*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3  *)
+    CID0: longword;  (*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0  *)
+    CID1: longword;  (*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1  *)
+    CID2: longword;  (*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2  *)
+    CID3: longword;  (*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3  *)
+  end;
+
+  DWT_Type = record
+    CTRL: longword;       (*!< Offset: 0x000 (R/W)  Control Register                           *)
+    CYCCNT: longword;     (*!< Offset: 0x004 (R/W)  Cycle Count Register                       *)
+    CPICNT: longword;     (*!< Offset: 0x008 (R/W)  CPI Count Register                         *)
+    EXCCNT: longword;     (*!< Offset: 0x00C (R/W)  Exception Overhead Count Register          *)
+    SLEEPCNT: longword;   (*!< Offset: 0x010 (R/W)  Sleep Count Register                       *)
+    LSUCNT: longword;     (*!< Offset: 0x014 (R/W)  LSU Count Register                         *)
+    FOLDCNT: longword;    (*!< Offset: 0x018 (R/W)  Folded-instruction Count Register          *)
+    PCSR: longword;       (*!< Offset: 0x01C (R/ )  Program Counter Sample Register            *)
+    COMP0: longword;      (*!< Offset: 0x020 (R/W)  Comparator Register 0                      *)
+    MASK0: longword;      (*!< Offset: 0x024 (R/W)  Mask Register 0                            *)
+    FUNCTION0: longword;  (*!< Offset: 0x028 (R/W)  Function Register 0                        *)
+    RESERVED0: array [0..0] of longword;
+    COMP1: longword;      (*!< Offset: 0x030 (R/W)  Comparator Register 1                      *)
+    MASK1: longword;      (*!< Offset: 0x034 (R/W)  Mask Register 1                            *)
+    FUNCTION1: longword;  (*!< Offset: 0x038 (R/W)  Function Register 1                        *)
+    RESERVED1: array [0..0] of longword;
+    COMP2: longword;      (*!< Offset: 0x040 (R/W)  Comparator Register 2                      *)
+    MASK2: longword;      (*!< Offset: 0x044 (R/W)  Mask Register 2                            *)
+    FUNCTION2: longword;  (*!< Offset: 0x048 (R/W)  Function Register 2                        *)
+    RESERVED2: array [0..0] of longword;
+    COMP3: longword;      (*!< Offset: 0x050 (R/W)  Comparator Register 3                      *)
+    MASK3: longword;      (*!< Offset: 0x054 (R/W)  Mask Register 3                            *)
+    FUNCTION3: longword;  (*!< Offset: 0x058 (R/W)  Function Register 3                        *)
+    RESERVED3: array [0..980] of longword;
+    LAR: longword;  (*!< Offset: 0xFB0 (  W)  Lock Access Register                       *)
+    LSR: longword;  (*!< Offset: 0xFB4 (R  )  Lock Status Register                       *)
+  end;
+
+  TPI_Type = record
+    SSPSR: longword;  (*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register      *)
+    CSPSR: longword;  (*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register  *)
+    RESERVED0: array [0..1] of longword;
+    ACPR: longword;  (*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register  *)
+    RESERVED1: array [0..54] of longword;
+    SPPR: longword;  (*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register  *)
+    RESERVED2: array [0..130] of longword;
+    FFSR: longword;  (*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register  *)
+    FFCR: longword;  (*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register  *)
+    FSCR: longword;  (*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register  *)
+    RESERVED3: array [0..758] of longword;
+    TRIGGER: longword;    (*!< Offset: 0xEE8 (R/ )  TRIGGER  *)
+    FIFO0: longword;      (*!< Offset: 0xEEC (R/ )  Integration ETM Data  *)
+    ITATBCTR2: longword;  (*!< Offset: 0xEF0 (R/ )  ITATBCTR2  *)
+    RESERVED4: array [0..0] of longword;
+    ITATBCTR0: longword;  (*!< Offset: 0xEF8 (R/ )  ITATBCTR0  *)
+    FIFO1: longword;      (*!< Offset: 0xEFC (R/ )  Integration ITM Data  *)
+    ITCTRL: longword;     (*!< Offset: 0xF00 (R/W)  Integration Mode Control  *)
+    RESERVED5: array [0..38] of longword;
+    CLAIMSET: longword;  (*!< Offset: 0xFA0 (R/W)  Claim tag set  *)
+    CLAIMCLR: longword;  (*!< Offset: 0xFA4 (R/W)  Claim tag clear  *)
+    RESERVED7: array [0..7] of longword;
+    DEVID: longword;    (*!< Offset: 0xFC8 (R/ )  TPIU_DEVID  *)
+    DEVTYPE: longword;  (*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE  *)
+  end;
+
+  MPU_Type = record
+    TYPE_: longword;    (*!< Offset: 0x000 (R/ )  MPU Type Register                               *)
+    CTRL: longword;     (*!< Offset: 0x004 (R/W)  MPU Control Register                            *)
+    RNR: longword;      (*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                      *)
+    RBAR: longword;     (*!< Offset: 0x00C (R/W)  MPU Region Base Address Register                *)
+    RASR: longword;     (*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register          *)
+    RBAR_A1: longword;  (*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register        *)
+    RASR_A1: longword;  (*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register  *)
+    RBAR_A2: longword;  (*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register        *)
+    RASR_A2: longword;  (*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register  *)
+    RBAR_A3: longword;  (*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register        *)
+    RASR_A3: longword;  (*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register  *)
+  end;
+
+  FPU_Type = record
+    RESERVED0: array [0..0] of longword;
+    FPCCR: longword;   (*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register                *)
+    FPCAR: longword;   (*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register                *)
+    FPDSCR: longword;  (*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register         *)
+    MVFR0: longword;   (*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                        *)
+    MVFR1: longword;   (*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                        *)
+    MVFR2: longword;   (*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                        *)
+  end;
+
+  CoreDebug_Type = record
+    DHCSR: longword;  (*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register     *)
+    DCRSR: longword;  (*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register         *)
+    DCRDR: longword;  (*!< Offset: 0x008 (R/W)  Debug Core Register Data Register             *)
+    DEMCR: longword;  (*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register  *)
+  end;
+
+(* Memory mapping of Cortex-M4 Hardware  *)
+
+const
+  SCS_BASE       = $E000E000;         (*!< System Control Space Base Address   *)
+  ITM_BASE       = $E0000000;         (*!< ITM Base Address                    *)
+  DWT_BASE       = $E0001000;         (*!< DWT Base Address                    *)
+  TPI_BASE       = $E0040000;         (*!< TPI Base Address                    *)
+  CoreDebug_BASE = $E000EDF0;         (*!< Core Debug Base Address             *)
+  SysTick_BASE   = SCS_BASE + $0010;  (*!< SysTick Base Address                *)
+  NVIC_BASE      = SCS_BASE + $0100;  (*!< NVIC Base Address                   *)
+  SCB_BASE       = SCS_BASE + $0D00;  (*!< System Control Block Base Address   *)
+
+var
+  SCnSCB:    SCnSCB_Type absolute SCS_BASE;       (*!< System control Register not in SCB  *)
+  SCB:       SCB_Type absolute SCB_BASE;          (*!< SCB configuration struct            *)
+  SysTick:   SysTick_Type absolute SysTick_BASE;  (*!< SysTick configuration struct        *)
+  NVIC:      NVIC_Type absolute NVIC_BASE;        (*!< NVIC configuration struct           *)
+  ITM:       ITM_Type absolute ITM_BASE;          (*!< ITM configuration struct            *)
+  DWT:       DWT_Type absolute DWT_BASE;          (*!< DWT configuration struct            *)
+  TPI:       TPI_Type absolute TPI_BASE;          (*!< TPI configuration struct            *)
+  CoreDebug: CoreDebug_Type absolute CoreDebug_BASE;  (*!< Core Debug configuration struct     *)
+
+type
+  TITM_Port = 0..31;
+
+
+procedure ITM_SendData(Port: TITM_Port; Data: char); inline;
+
+implementation
+
+procedure ITM_SendData(Port: TITM_Port; Data: char);
+begin
+  if (((ITM.TCR and 1) <> 0) and ((ITM.TER and 1) <> 0)) then
+  begin
+    while (ITM.PORT[integer(Port)].u32 = 0) do ;
+    ITM.PORT[integer(Port)].u8 := byte(Data);
+  end;
+end;
+
+end.
diff --git a/rtl/freertos/arm/stm32f103xe.pp b/rtl/freertos/arm/stm32f103xe.pp
new file mode 100644
index 0000000000..a7ed045a2b
--- /dev/null
+++ b/rtl/freertos/arm/stm32f103xe.pp
@@ -0,0 +1,924 @@
+unit stm32f103xe;
+interface
+{$PACKRECORDS C}
+{$GOTO ON}
+{$SCOPEDENUMS ON}
+
+type
+  TIRQn_Enum = (
+    NonMaskableInt_IRQn = -14,        
+    HardFault_IRQn = -13,             
+    MemoryManagement_IRQn = -12,      
+    BusFault_IRQn = -11,              
+    UsageFault_IRQn = -10,            
+    SVCall_IRQn = -5,                 
+    DebugMonitor_IRQn = -4,           
+    PendSV_IRQn = -2,                 
+    SysTick_IRQn = -1,                
+    WWDG_IRQn   = 0,                  
+    PVD_IRQn    = 1,                  
+    TAMPER_IRQn = 2,                  
+    RTC_IRQn    = 3,                  
+    FLASH_IRQn  = 4,                  
+    RCC_IRQn    = 5,                  
+    EXTI0_IRQn  = 6,                  
+    EXTI1_IRQn  = 7,                  
+    EXTI2_IRQn  = 8,                  
+    EXTI3_IRQn  = 9,                  
+    EXTI4_IRQn  = 10,                 
+    DMA1_Channel1_IRQn = 11,          
+    DMA1_Channel2_IRQn = 12,          
+    DMA1_Channel3_IRQn = 13,          
+    DMA1_Channel4_IRQn = 14,          
+    DMA1_Channel5_IRQn = 15,          
+    DMA1_Channel6_IRQn = 16,          
+    DMA1_Channel7_IRQn = 17,          
+    ADC1_2_IRQn = 18,                 
+    USB_HP_CAN1_TX_IRQn = 19,         
+    USB_LP_CAN1_RX0_IRQn = 20,        
+    CAN1_RX1_IRQn = 21,               
+    CAN1_SCE_IRQn = 22,               
+    EXTI9_5_IRQn = 23,                
+    TIM1_BRK_IRQn = 24,               
+    TIM1_UP_IRQn = 25,                
+    TIM1_TRG_COM_IRQn = 26,           
+    TIM1_CC_IRQn = 27,                
+    TIM2_IRQn   = 28,                 
+    TIM3_IRQn   = 29,                 
+    TIM4_IRQn   = 30,                 
+    I2C1_EV_IRQn = 31,                
+    I2C1_ER_IRQn = 32,                
+    I2C2_EV_IRQn = 33,                
+    I2C2_ER_IRQn = 34,                
+    SPI1_IRQn   = 35,                 
+    SPI2_IRQn   = 36,                 
+    USART1_IRQn = 37,                 
+    USART2_IRQn = 38,                 
+    USART3_IRQn = 39,                 
+    EXTI15_10_IRQn = 40,              
+    RTC_Alarm_IRQn = 41,              
+    USBWakeUp_IRQn = 42,              
+    TIM8_BRK_IRQn = 43,               
+    TIM8_UP_IRQn = 44,                
+    TIM8_TRG_COM_IRQn = 45,           
+    TIM8_CC_IRQn = 46,                
+    ADC3_IRQn   = 47,                 
+    FSMC_IRQn   = 48,                 
+    SDIO_IRQn   = 49,                 
+    TIM5_IRQn   = 50,                 
+    SPI3_IRQn   = 51,                 
+    UART4_IRQn  = 52,                 
+    UART5_IRQn  = 53,                 
+    TIM6_IRQn   = 54,                 
+    TIM7_IRQn   = 55,                 
+    DMA2_Channel1_IRQn = 56,          
+    DMA2_Channel2_IRQn = 57,          
+    DMA2_Channel3_IRQn = 58,          
+    DMA2_Channel4_5_IRQn = 59         
+  );
+
+  TADC_Registers = record
+    SR          : longword;
+    CR1         : longword;
+    CR2         : longword;
+    SMPR1       : longword;
+    SMPR2       : longword;
+    JOFR1       : longword;
+    JOFR2       : longword;
+    JOFR3       : longword;
+    JOFR4       : longword;
+    HTR         : longword;
+    LTR         : longword;
+    SQR1        : longword;
+    SQR2        : longword;
+    SQR3        : longword;
+    JSQR        : longword;
+    JDR1        : longword;
+    JDR2        : longword;
+    JDR3        : longword;
+    JDR4        : longword;
+    DR          : longword;
+  end;
+
+  TADC_Common_Registers = record
+    SR          : longword;
+    CR1         : longword;
+    CR2         : longword;
+    RESERVED    : array[0..15] of longword;
+    DR          : longword;
+  end;
+
+  TBKP_Registers = record
+    RESERVED0   : longword;
+    DR1         : longword;
+    DR2         : longword;
+    DR3         : longword;
+    DR4         : longword;
+    DR5         : longword;
+    DR6         : longword;
+    DR7         : longword;
+    DR8         : longword;
+    DR9         : longword;
+    DR10        : longword;
+    RTCCR       : longword;
+    CR          : longword;
+    CSR         : longword;
+    RESERVED13  : array[0..1] of longword;
+    DR11        : longword;
+    DR12        : longword;
+    DR13        : longword;
+    DR14        : longword;
+    DR15        : longword;
+    DR16        : longword;
+    DR17        : longword;
+    DR18        : longword;
+    DR19        : longword;
+    DR20        : longword;
+    DR21        : longword;
+    DR22        : longword;
+    DR23        : longword;
+    DR24        : longword;
+    DR25        : longword;
+    DR26        : longword;
+    DR27        : longword;
+    DR28        : longword;
+    DR29        : longword;
+    DR30        : longword;
+    DR31        : longword;
+    DR32        : longword;
+    DR33        : longword;
+    DR34        : longword;
+    DR35        : longword;
+    DR36        : longword;
+    DR37        : longword;
+    DR38        : longword;
+    DR39        : longword;
+    DR40        : longword;
+    DR41        : longword;
+    DR42        : longword;
+  end;
+
+  TCAN_TxMailBox_Registers = record
+    TIR         : longword;
+    TDTR        : longword;
+    TDLR        : longword;
+    TDHR        : longword;
+  end;
+
+  TCAN_FIFOMailBox_Registers = record
+    RIR         : longword;
+    RDTR        : longword;
+    RDLR        : longword;
+    RDHR        : longword;
+  end;
+
+  TCAN_FilterRegister_Registers = record
+    FR1         : longword;
+    FR2         : longword;
+  end;
+
+  TCAN_Registers = record
+    MCR         : longword;
+    MSR         : longword;
+    TSR         : longword;
+    RF0R        : longword;
+    RF1R        : longword;
+    IER         : longword;
+    ESR         : longword;
+    BTR         : longword;
+    RESERVED0   : array[0..87] of longword;
+    sTxMailBox  : array[0..2] of TCAN_TxMailBox_Registers;
+    sFIFOMailBox : array[0..1] of TCAN_FIFOMailBox_Registers;
+    RESERVED1   : array[0..11] of longword;
+    FMR         : longword;
+    FM1R        : longword;
+    RESERVED2   : longword;
+    FS1R        : longword;
+    RESERVED3   : longword;
+    FFA1R       : longword;
+    RESERVED4   : longword;
+    FA1R        : longword;
+    RESERVED5   : array[0..7] of longword;
+    sFilterRegister : array[0..13] of TCAN_FilterRegister_Registers;
+  end;
+
+  TCRC_Registers = record
+    DR          : longword;
+    IDR         : byte;
+    RESERVED0   : byte;
+    RESERVED1   : word;
+    CR          : longword;
+  end;
+
+  TDAC_Registers = record
+    CR          : longword;
+    SWTRIGR     : longword;
+    DHR12R1     : longword;
+    DHR12L1     : longword;
+    DHR8R1      : longword;
+    DHR12R2     : longword;
+    DHR12L2     : longword;
+    DHR8R2      : longword;
+    DHR12RD     : longword;
+    DHR12LD     : longword;
+    DHR8RD      : longword;
+    DOR1        : longword;
+    DOR2        : longword;
+  end;
+
+  TDBGMCU_Registers = record
+    IDCODE      : longword;
+    CR          : longword;
+  end;
+
+  TDMA_Channel_Registers = record
+    CCR         : longword;
+    CNDTR       : longword;
+    CPAR        : longword;
+    CMAR        : longword;
+  end;
+
+  TDMA_Registers = record
+    ISR         : longword;
+    IFCR        : longword;
+  end;
+
+  TEXTI_Registers = record
+    IMR         : longword;
+    EMR         : longword;
+    RTSR        : longword;
+    FTSR        : longword;
+    SWIER       : longword;
+    PR          : longword;
+  end;
+
+  TFLASH_Registers = record
+    ACR         : longword;
+    KEYR        : longword;
+    OPTKEYR     : longword;
+    SR          : longword;
+    CR          : longword;
+    AR          : longword;
+    RESERVED    : longword;
+    OBR         : longword;
+    WRPR        : longword;
+  end;
+
+  TOB_Registers = record
+    RDP         : word;
+    USER        : word;
+    Data0       : word;
+    Data1       : word;
+    WRP0        : word;
+    WRP1        : word;
+    WRP2        : word;
+    WRP3        : word;
+  end;
+
+  TFSMC_Bank1_Registers = record
+    BTCR        : array[0..7] of longword;
+  end;
+
+  TFSMC_Bank1E_Registers = record
+    BWTR        : array[0..6] of longword;
+  end;
+
+  TFSMC_Bank2_3_Registers = record
+    PCR2        : longword;
+    SR2         : longword;
+    PMEM2       : longword;
+    PATT2       : longword;
+    RESERVED0   : longword;
+    ECCR2       : longword;
+    RESERVED1   : longword;
+    RESERVED2   : longword;
+    PCR3        : longword;
+    SR3         : longword;
+    PMEM3       : longword;
+    PATT3       : longword;
+    RESERVED3   : longword;
+    ECCR3       : longword;
+  end;
+
+  TFSMC_Bank4_Registers = record
+    PCR4        : longword;
+    SR4         : longword;
+    PMEM4       : longword;
+    PATT4       : longword;
+    PIO4        : longword;
+  end;
+
+  TGPIO_Registers = record
+    CRL         : longword;
+    CRH         : longword;
+    IDR         : longword;
+    ODR         : longword;
+    BSRR        : longword;
+    BRR         : longword;
+    LCKR        : longword;
+  end;
+
+  TAFIO_Registers = record
+    EVCR        : longword;
+    MAPR        : longword;
+    EXTICR      : array[0..3] of longword;
+    RESERVED0   : longword;
+    MAPR2       : longword;
+  end;
+
+  TI2C_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    OAR1        : longword;
+    OAR2        : longword;
+    DR          : longword;
+    SR1         : longword;
+    SR2         : longword;
+    CCR         : longword;
+    TRISE       : longword;
+  end;
+
+  TIWDG_Registers = record
+    KR          : longword;
+    PR          : longword;
+    RLR         : longword;
+    SR          : longword;
+  end;
+
+  TPWR_Registers = record
+    CR          : longword;
+    CSR         : longword;
+  end;
+
+  TRCC_Registers = record
+    CR          : longword;
+    CFGR        : longword;
+    CIR         : longword;
+    APB2RSTR    : longword;
+    APB1RSTR    : longword;
+    AHBENR      : longword;
+    APB2ENR     : longword;
+    APB1ENR     : longword;
+    BDCR        : longword;
+    CSR         : longword;
+  end;
+
+  TRTC_Registers = record
+    CRH         : longword;
+    CRL         : longword;
+    PRLH        : longword;
+    PRLL        : longword;
+    DIVH        : longword;
+    DIVL        : longword;
+    CNTH        : longword;
+    CNTL        : longword;
+    ALRH        : longword;
+    ALRL        : longword;
+  end;
+
+  TSDIO_Registers = record
+    POWER       : longword;
+    CLKCR       : longword;
+    ARG         : longword;
+    CMD         : longword;
+    RESPCMD     : longword;
+    RESP1       : longword;
+    RESP2       : longword;
+    RESP3       : longword;
+    RESP4       : longword;
+    DTIMER      : longword;
+    DLEN        : longword;
+    DCTRL       : longword;
+    DCOUNT      : longword;
+    STA         : longword;
+    ICR         : longword;
+    MASK        : longword;
+    RESERVED0   : array[0..1] of longword;
+    FIFOCNT     : longword;
+    RESERVED1   : array[0..12] of longword;
+    FIFO        : longword;
+  end;
+
+  TSPI_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    SR          : longword;
+    DR          : longword;
+    CRCPR       : longword;
+    RXCRCR      : longword;
+    TXCRCR      : longword;
+    I2SCFGR     : longword;
+    I2SPR       : longword;
+  end;
+
+  TTIM_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    SMCR        : longword;
+    DIER        : longword;
+    SR          : longword;
+    EGR         : longword;
+    CCMR1       : longword;
+    CCMR2       : longword;
+    CCER        : longword;
+    CNT         : longword;
+    PSC         : longword;
+    ARR         : longword;
+    RCR         : longword;
+    CCR1        : longword;
+    CCR2        : longword;
+    CCR3        : longword;
+    CCR4        : longword;
+    BDTR        : longword;
+    DCR         : longword;
+    DMAR        : longword;
+    &OR         : longword;
+  end;
+
+  TUSART_Registers = record
+    SR          : longword;
+    DR          : longword;
+    BRR         : longword;
+    CR1         : longword;
+    CR2         : longword;
+    CR3         : longword;
+    GTPR        : longword;
+  end;
+
+  TUSB_Registers = record
+    EP0R        : word;
+    RESERVED0   : word;
+    EP1R        : word;
+    RESERVED1   : word;
+    EP2R        : word;
+    RESERVED2   : word;
+    EP3R        : word;
+    RESERVED3   : word;
+    EP4R        : word;
+    RESERVED4   : word;
+    EP5R        : word;
+    RESERVED5   : word;
+    EP6R        : word;
+    RESERVED6   : word;
+    EP7R        : word;
+    RESERVED7   : array[0..16] of word;
+    CNTR        : word;
+    RESERVED8   : word;
+    ISTR        : word;
+    RESERVED9   : word;
+    FNR         : word;
+    RESERVEDA   : word;
+    DADDR       : word;
+    RESERVEDB   : word;
+    BTABLE      : word;
+    RESERVEDC   : word;
+  end;
+
+  TWWDG_Registers = record
+    CR          : longword;
+    CFR         : longword;
+    SR          : longword;
+  end;
+
+const
+  FLASH_BASE    = $08000000;
+  SRAM_BASE     = $20000000;
+  PERIPH_BASE   = $40000000;
+  SRAM_BB_BASE  = $22000000;
+  PERIPH_BB_BASE= $42000000;
+  FSMC_BASE     = $60000000;
+  FSMC_R_BASE   = $A0000000;
+  APB1PERIPH_BASE= PERIPH_BASE;
+  APB2PERIPH_BASE= PERIPH_BASE + $00010000;
+  AHBPERIPH_BASE= PERIPH_BASE + $00020000;
+  TIM2_BASE     = APB1PERIPH_BASE + $00000000;
+  TIM3_BASE     = APB1PERIPH_BASE + $00000400;
+  TIM4_BASE     = APB1PERIPH_BASE + $00000800;
+  TIM5_BASE     = APB1PERIPH_BASE + $00000C00;
+  TIM6_BASE     = APB1PERIPH_BASE + $00001000;
+  TIM7_BASE     = APB1PERIPH_BASE + $00001400;
+  RTC_BASE      = APB1PERIPH_BASE + $00002800;
+  WWDG_BASE     = APB1PERIPH_BASE + $00002C00;
+  IWDG_BASE     = APB1PERIPH_BASE + $00003000;
+  SPI2_BASE     = APB1PERIPH_BASE + $00003800;
+  SPI3_BASE     = APB1PERIPH_BASE + $00003C00;
+  USART2_BASE   = APB1PERIPH_BASE + $00004400;
+  USART3_BASE   = APB1PERIPH_BASE + $00004800;
+  UART4_BASE    = APB1PERIPH_BASE + $00004C00;
+  UART5_BASE    = APB1PERIPH_BASE + $00005000;
+  I2C1_BASE     = APB1PERIPH_BASE + $00005400;
+  I2C2_BASE     = APB1PERIPH_BASE + $00005800;
+  CAN1_BASE     = APB1PERIPH_BASE + $00006400;
+  BKP_BASE      = APB1PERIPH_BASE + $00006C00;
+  PWR_BASE      = APB1PERIPH_BASE + $00007000;
+  DAC_BASE      = APB1PERIPH_BASE + $00007400;
+  AFIO_BASE     = APB2PERIPH_BASE + $00000000;
+  EXTI_BASE     = APB2PERIPH_BASE + $00000400;
+  GPIOA_BASE    = APB2PERIPH_BASE + $00000800;
+  GPIOB_BASE    = APB2PERIPH_BASE + $00000C00;
+  GPIOC_BASE    = APB2PERIPH_BASE + $00001000;
+  GPIOD_BASE    = APB2PERIPH_BASE + $00001400;
+  GPIOE_BASE    = APB2PERIPH_BASE + $00001800;
+  GPIOF_BASE    = APB2PERIPH_BASE + $00001C00;
+  GPIOG_BASE    = APB2PERIPH_BASE + $00002000;
+  ADC1_BASE     = APB2PERIPH_BASE + $00002400;
+  ADC2_BASE     = APB2PERIPH_BASE + $00002800;
+  TIM1_BASE     = APB2PERIPH_BASE + $00002C00;
+  SPI1_BASE     = APB2PERIPH_BASE + $00003000;
+  TIM8_BASE     = APB2PERIPH_BASE + $00003400;
+  USART1_BASE   = APB2PERIPH_BASE + $00003800;
+  ADC3_BASE     = APB2PERIPH_BASE + $00003C00;
+  SDIO_BASE     = PERIPH_BASE + $00018000;
+  DMA1_BASE     = AHBPERIPH_BASE + $00000000;
+  DMA1_Channel1_BASE= AHBPERIPH_BASE + $00000008;
+  DMA1_Channel2_BASE= AHBPERIPH_BASE + $0000001C;
+  DMA1_Channel3_BASE= AHBPERIPH_BASE + $00000030;
+  DMA1_Channel4_BASE= AHBPERIPH_BASE + $00000044;
+  DMA1_Channel5_BASE= AHBPERIPH_BASE + $00000058;
+  DMA1_Channel6_BASE= AHBPERIPH_BASE + $0000006C;
+  DMA1_Channel7_BASE= AHBPERIPH_BASE + $00000080;
+  DMA2_BASE     = AHBPERIPH_BASE + $00000400;
+  DMA2_Channel1_BASE= AHBPERIPH_BASE + $00000408;
+  DMA2_Channel2_BASE= AHBPERIPH_BASE + $0000041C;
+  DMA2_Channel3_BASE= AHBPERIPH_BASE + $00000430;
+  DMA2_Channel4_BASE= AHBPERIPH_BASE + $00000444;
+  DMA2_Channel5_BASE= AHBPERIPH_BASE + $00000458;
+  RCC_BASE      = AHBPERIPH_BASE + $00001000;
+  CRC_BASE      = AHBPERIPH_BASE + $00003000;
+  FLASH_R_BASE  = AHBPERIPH_BASE + $00002000;
+  FLASHSIZE_BASE= $1FFFF7E0;
+  UID_BASE      = $1FFFF7E8;
+  OB_BASE       = $1FFFF800;
+  FSMC_BANK1_R_BASE= FSMC_R_BASE + $00000000;
+  FSMC_BANK1E_R_BASE= FSMC_R_BASE + $00000104;
+  FSMC_BANK2_3_R_BASE= FSMC_R_BASE + $00000060;
+  FSMC_BANK4_R_BASE= FSMC_R_BASE + $000000A0;
+  DBGMCU_BASE   = $E0042000;
+  USB_BASE      = APB1PERIPH_BASE + $00005C00;
+
+var
+  TIM2          : TTIM_Registers absolute TIM2_BASE;
+  TIM3          : TTIM_Registers absolute TIM3_BASE;
+  TIM4          : TTIM_Registers absolute TIM4_BASE;
+  TIM5          : TTIM_Registers absolute TIM5_BASE;
+  TIM6          : TTIM_Registers absolute TIM6_BASE;
+  TIM7          : TTIM_Registers absolute TIM7_BASE;
+  RTC           : TRTC_Registers absolute RTC_BASE;
+  WWDG          : TWWDG_Registers absolute WWDG_BASE;
+  IWDG          : TIWDG_Registers absolute IWDG_BASE;
+  SPI2          : TSPI_Registers absolute SPI2_BASE;
+  SPI3          : TSPI_Registers absolute SPI3_BASE;
+  USART2        : TUSART_Registers absolute USART2_BASE;
+  USART3        : TUSART_Registers absolute USART3_BASE;
+  UART4         : TUSART_Registers absolute UART4_BASE;
+  UART5         : TUSART_Registers absolute UART5_BASE;
+  I2C1          : TI2C_Registers absolute I2C1_BASE;
+  I2C2          : TI2C_Registers absolute I2C2_BASE;
+  USB           : TUSB_Registers absolute USB_BASE;
+  CAN1          : TCAN_Registers absolute CAN1_BASE;
+  BKP           : TBKP_Registers absolute BKP_BASE;
+  PWR           : TPWR_Registers absolute PWR_BASE;
+  DAC1          : TDAC_Registers absolute DAC_BASE;
+  DAC           : TDAC_Registers absolute DAC_BASE;
+  AFIO          : TAFIO_Registers absolute AFIO_BASE;
+  EXTI          : TEXTI_Registers absolute EXTI_BASE;
+  GPIOA         : TGPIO_Registers absolute GPIOA_BASE;
+  GPIOB         : TGPIO_Registers absolute GPIOB_BASE;
+  GPIOC         : TGPIO_Registers absolute GPIOC_BASE;
+  GPIOD         : TGPIO_Registers absolute GPIOD_BASE;
+  GPIOE         : TGPIO_Registers absolute GPIOE_BASE;
+  GPIOF         : TGPIO_Registers absolute GPIOF_BASE;
+  GPIOG         : TGPIO_Registers absolute GPIOG_BASE;
+  ADC1          : TADC_Registers absolute ADC1_BASE;
+  ADC2          : TADC_Registers absolute ADC2_BASE;
+  ADC3          : TADC_Registers absolute ADC3_BASE;
+  ADC12_COMMON  : TADC_Common_Registers absolute ADC1_BASE;
+  TIM1          : TTIM_Registers absolute TIM1_BASE;
+  SPI1          : TSPI_Registers absolute SPI1_BASE;
+  TIM8          : TTIM_Registers absolute TIM8_BASE;
+  USART1        : TUSART_Registers absolute USART1_BASE;
+  SDIO          : TSDIO_Registers absolute SDIO_BASE;
+  DMA1          : TDMA_Registers absolute DMA1_BASE;
+  DMA2          : TDMA_Registers absolute DMA2_BASE;
+  DMA1_Channel1 : TDMA_Channel_Registers absolute DMA1_Channel1_BASE;
+  DMA1_Channel2 : TDMA_Channel_Registers absolute DMA1_Channel2_BASE;
+  DMA1_Channel3 : TDMA_Channel_Registers absolute DMA1_Channel3_BASE;
+  DMA1_Channel4 : TDMA_Channel_Registers absolute DMA1_Channel4_BASE;
+  DMA1_Channel5 : TDMA_Channel_Registers absolute DMA1_Channel5_BASE;
+  DMA1_Channel6 : TDMA_Channel_Registers absolute DMA1_Channel6_BASE;
+  DMA1_Channel7 : TDMA_Channel_Registers absolute DMA1_Channel7_BASE;
+  DMA2_Channel1 : TDMA_Channel_Registers absolute DMA2_Channel1_BASE;
+  DMA2_Channel2 : TDMA_Channel_Registers absolute DMA2_Channel2_BASE;
+  DMA2_Channel3 : TDMA_Channel_Registers absolute DMA2_Channel3_BASE;
+  DMA2_Channel4 : TDMA_Channel_Registers absolute DMA2_Channel4_BASE;
+  DMA2_Channel5 : TDMA_Channel_Registers absolute DMA2_Channel5_BASE;
+  RCC           : TRCC_Registers absolute RCC_BASE;
+  CRC           : TCRC_Registers absolute CRC_BASE;
+  FLASH         : TFLASH_Registers absolute FLASH_R_BASE;
+  OB            : TOB_Registers absolute OB_BASE;
+  FSMC_Bank1    : TFSMC_Bank1_Registers absolute FSMC_BANK1_R_BASE;
+  FSMC_Bank1E   : TFSMC_Bank1E_Registers absolute FSMC_BANK1E_R_BASE;
+  FSMC_Bank2_3  : TFSMC_Bank2_3_Registers absolute FSMC_BANK2_3_R_BASE;
+  FSMC_Bank4    : TFSMC_Bank4_Registers absolute FSMC_BANK4_R_BASE;
+  DBGMCU        : TDBGMCU_Registers absolute DBGMCU_BASE;
+
+implementation
+
+procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
+procedure HardFault_interrupt; external name 'HardFault_interrupt';
+procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SVCall_interrupt; external name 'SVCall_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendSV_interrupt; external name 'PendSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure WWDG_interrupt; external name 'WWDG_interrupt';
+procedure PVD_interrupt; external name 'PVD_interrupt';
+procedure TAMPER_interrupt; external name 'TAMPER_interrupt';
+procedure RTC_interrupt; external name 'RTC_interrupt';
+procedure FLASH_interrupt; external name 'FLASH_interrupt';
+procedure RCC_interrupt; external name 'RCC_interrupt';
+procedure EXTI0_interrupt; external name 'EXTI0_interrupt';
+procedure EXTI1_interrupt; external name 'EXTI1_interrupt';
+procedure EXTI2_interrupt; external name 'EXTI2_interrupt';
+procedure EXTI3_interrupt; external name 'EXTI3_interrupt';
+procedure EXTI4_interrupt; external name 'EXTI4_interrupt';
+procedure DMA1_Channel1_interrupt; external name 'DMA1_Channel1_interrupt';
+procedure DMA1_Channel2_interrupt; external name 'DMA1_Channel2_interrupt';
+procedure DMA1_Channel3_interrupt; external name 'DMA1_Channel3_interrupt';
+procedure DMA1_Channel4_interrupt; external name 'DMA1_Channel4_interrupt';
+procedure DMA1_Channel5_interrupt; external name 'DMA1_Channel5_interrupt';
+procedure DMA1_Channel6_interrupt; external name 'DMA1_Channel6_interrupt';
+procedure DMA1_Channel7_interrupt; external name 'DMA1_Channel7_interrupt';
+procedure ADC1_2_interrupt; external name 'ADC1_2_interrupt';
+procedure USB_HP_CAN1_TX_interrupt; external name 'USB_HP_CAN1_TX_interrupt';
+procedure USB_LP_CAN1_RX0_interrupt; external name 'USB_LP_CAN1_RX0_interrupt';
+procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt';
+procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt';
+procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt';
+procedure TIM1_BRK_interrupt; external name 'TIM1_BRK_interrupt';
+procedure TIM1_UP_interrupt; external name 'TIM1_UP_interrupt';
+procedure TIM1_TRG_COM_interrupt; external name 'TIM1_TRG_COM_interrupt';
+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
+procedure TIM2_interrupt; external name 'TIM2_interrupt';
+procedure TIM3_interrupt; external name 'TIM3_interrupt';
+procedure TIM4_interrupt; external name 'TIM4_interrupt';
+procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt';
+procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt';
+procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt';
+procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt';
+procedure SPI1_interrupt; external name 'SPI1_interrupt';
+procedure SPI2_interrupt; external name 'SPI2_interrupt';
+procedure USART1_interrupt; external name 'USART1_interrupt';
+procedure USART2_interrupt; external name 'USART2_interrupt';
+procedure USART3_interrupt; external name 'USART3_interrupt';
+procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt';
+procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt';
+procedure USBWakeUp_interrupt; external name 'USBWakeUp_interrupt';
+procedure TIM8_BRK_interrupt; external name 'TIM8_BRK_interrupt';
+procedure TIM8_UP_interrupt; external name 'TIM8_UP_interrupt';
+procedure TIM8_TRG_COM_interrupt; external name 'TIM8_TRG_COM_interrupt';
+procedure TIM8_CC_interrupt; external name 'TIM8_CC_interrupt';
+procedure ADC3_interrupt; external name 'ADC3_interrupt';
+procedure FSMC_interrupt; external name 'FSMC_interrupt';
+procedure SDIO_interrupt; external name 'SDIO_interrupt';
+procedure TIM5_interrupt; external name 'TIM5_interrupt';
+procedure SPI3_interrupt; external name 'SPI3_interrupt';
+procedure UART4_interrupt; external name 'UART4_interrupt';
+procedure UART5_interrupt; external name 'UART5_interrupt';
+procedure TIM6_interrupt; external name 'TIM6_interrupt';
+procedure TIM7_interrupt; external name 'TIM7_interrupt';
+procedure DMA2_Channel1_interrupt; external name 'DMA2_Channel1_interrupt';
+procedure DMA2_Channel2_interrupt; external name 'DMA2_Channel2_interrupt';
+procedure DMA2_Channel3_interrupt; external name 'DMA2_Channel3_interrupt';
+procedure DMA2_Channel4_5_interrupt; external name 'DMA2_Channel4_5_interrupt';
+
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+  .section ".init.interrupt_vectors"
+  interrupt_vectors:
+  .long _stack_top
+  .long Startup
+  .long NonMaskableInt_interrupt
+  .long HardFault_interrupt
+  .long MemoryManagement_interrupt
+  .long BusFault_interrupt
+  .long UsageFault_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long SVCall_interrupt
+  .long DebugMonitor_interrupt
+  .long 0
+  .long PendSV_interrupt
+  .long SysTick_interrupt
+  .long WWDG_interrupt
+  .long PVD_interrupt
+  .long TAMPER_interrupt
+  .long RTC_interrupt
+  .long FLASH_interrupt
+  .long RCC_interrupt
+  .long EXTI0_interrupt
+  .long EXTI1_interrupt
+  .long EXTI2_interrupt
+  .long EXTI3_interrupt
+  .long EXTI4_interrupt
+  .long DMA1_Channel1_interrupt
+  .long DMA1_Channel2_interrupt
+  .long DMA1_Channel3_interrupt
+  .long DMA1_Channel4_interrupt
+  .long DMA1_Channel5_interrupt
+  .long DMA1_Channel6_interrupt
+  .long DMA1_Channel7_interrupt
+  .long ADC1_2_interrupt
+  .long USB_HP_CAN1_TX_interrupt
+  .long USB_LP_CAN1_RX0_interrupt
+  .long CAN1_RX1_interrupt
+  .long CAN1_SCE_interrupt
+  .long EXTI9_5_interrupt
+  .long TIM1_BRK_interrupt
+  .long TIM1_UP_interrupt
+  .long TIM1_TRG_COM_interrupt
+  .long TIM1_CC_interrupt
+  .long TIM2_interrupt
+  .long TIM3_interrupt
+  .long TIM4_interrupt
+  .long I2C1_EV_interrupt
+  .long I2C1_ER_interrupt
+  .long I2C2_EV_interrupt
+  .long I2C2_ER_interrupt
+  .long SPI1_interrupt
+  .long SPI2_interrupt
+  .long USART1_interrupt
+  .long USART2_interrupt
+  .long USART3_interrupt
+  .long EXTI15_10_interrupt
+  .long RTC_Alarm_interrupt
+  .long USBWakeUp_interrupt
+  .long TIM8_BRK_interrupt
+  .long TIM8_UP_interrupt
+  .long TIM8_TRG_COM_interrupt
+  .long TIM8_CC_interrupt
+  .long ADC3_interrupt
+  .long FSMC_interrupt
+  .long SDIO_interrupt
+  .long TIM5_interrupt
+  .long SPI3_interrupt
+  .long UART4_interrupt
+  .long UART5_interrupt
+  .long TIM6_interrupt
+  .long TIM7_interrupt
+  .long DMA2_Channel1_interrupt
+  .long DMA2_Channel2_interrupt
+  .long DMA2_Channel3_interrupt
+  .long DMA2_Channel4_5_interrupt
+
+  .weak NonMaskableInt_interrupt
+  .weak HardFault_interrupt
+  .weak MemoryManagement_interrupt
+  .weak BusFault_interrupt
+  .weak UsageFault_interrupt
+  .weak SVCall_interrupt
+  .weak DebugMonitor_interrupt
+  .weak PendSV_interrupt
+  .weak SysTick_interrupt
+  .weak WWDG_interrupt
+  .weak PVD_interrupt
+  .weak TAMPER_interrupt
+  .weak RTC_interrupt
+  .weak FLASH_interrupt
+  .weak RCC_interrupt
+  .weak EXTI0_interrupt
+  .weak EXTI1_interrupt
+  .weak EXTI2_interrupt
+  .weak EXTI3_interrupt
+  .weak EXTI4_interrupt
+  .weak DMA1_Channel1_interrupt
+  .weak DMA1_Channel2_interrupt
+  .weak DMA1_Channel3_interrupt
+  .weak DMA1_Channel4_interrupt
+  .weak DMA1_Channel5_interrupt
+  .weak DMA1_Channel6_interrupt
+  .weak DMA1_Channel7_interrupt
+  .weak ADC1_2_interrupt
+  .weak USB_HP_CAN1_TX_interrupt
+  .weak USB_LP_CAN1_RX0_interrupt
+  .weak CAN1_RX1_interrupt
+  .weak CAN1_SCE_interrupt
+  .weak EXTI9_5_interrupt
+  .weak TIM1_BRK_interrupt
+  .weak TIM1_UP_interrupt
+  .weak TIM1_TRG_COM_interrupt
+  .weak TIM1_CC_interrupt
+  .weak TIM2_interrupt
+  .weak TIM3_interrupt
+  .weak TIM4_interrupt
+  .weak I2C1_EV_interrupt
+  .weak I2C1_ER_interrupt
+  .weak I2C2_EV_interrupt
+  .weak I2C2_ER_interrupt
+  .weak SPI1_interrupt
+  .weak SPI2_interrupt
+  .weak USART1_interrupt
+  .weak USART2_interrupt
+  .weak USART3_interrupt
+  .weak EXTI15_10_interrupt
+  .weak RTC_Alarm_interrupt
+  .weak USBWakeUp_interrupt
+  .weak TIM8_BRK_interrupt
+  .weak TIM8_UP_interrupt
+  .weak TIM8_TRG_COM_interrupt
+  .weak TIM8_CC_interrupt
+  .weak ADC3_interrupt
+  .weak FSMC_interrupt
+  .weak SDIO_interrupt
+  .weak TIM5_interrupt
+  .weak SPI3_interrupt
+  .weak UART4_interrupt
+  .weak UART5_interrupt
+  .weak TIM6_interrupt
+  .weak TIM7_interrupt
+  .weak DMA2_Channel1_interrupt
+  .weak DMA2_Channel2_interrupt
+  .weak DMA2_Channel3_interrupt
+  .weak DMA2_Channel4_5_interrupt
+
+  .set NonMaskableInt_interrupt, Haltproc
+  .set HardFault_interrupt, Haltproc
+  .set MemoryManagement_interrupt, Haltproc
+  .set BusFault_interrupt, Haltproc
+  .set UsageFault_interrupt, Haltproc
+  .set SVCall_interrupt, Haltproc
+  .set DebugMonitor_interrupt, Haltproc
+  .set PendSV_interrupt, Haltproc
+  .set SysTick_interrupt, Haltproc
+  .set WWDG_interrupt, Haltproc
+  .set PVD_interrupt, Haltproc
+  .set TAMPER_interrupt, Haltproc
+  .set RTC_interrupt, Haltproc
+  .set FLASH_interrupt, Haltproc
+  .set RCC_interrupt, Haltproc
+  .set EXTI0_interrupt, Haltproc
+  .set EXTI1_interrupt, Haltproc
+  .set EXTI2_interrupt, Haltproc
+  .set EXTI3_interrupt, Haltproc
+  .set EXTI4_interrupt, Haltproc
+  .set DMA1_Channel1_interrupt, Haltproc
+  .set DMA1_Channel2_interrupt, Haltproc
+  .set DMA1_Channel3_interrupt, Haltproc
+  .set DMA1_Channel4_interrupt, Haltproc
+  .set DMA1_Channel5_interrupt, Haltproc
+  .set DMA1_Channel6_interrupt, Haltproc
+  .set DMA1_Channel7_interrupt, Haltproc
+  .set ADC1_2_interrupt, Haltproc
+  .set USB_HP_CAN1_TX_interrupt, Haltproc
+  .set USB_LP_CAN1_RX0_interrupt, Haltproc
+  .set CAN1_RX1_interrupt, Haltproc
+  .set CAN1_SCE_interrupt, Haltproc
+  .set EXTI9_5_interrupt, Haltproc
+  .set TIM1_BRK_interrupt, Haltproc
+  .set TIM1_UP_interrupt, Haltproc
+  .set TIM1_TRG_COM_interrupt, Haltproc
+  .set TIM1_CC_interrupt, Haltproc
+  .set TIM2_interrupt, Haltproc
+  .set TIM3_interrupt, Haltproc
+  .set TIM4_interrupt, Haltproc
+  .set I2C1_EV_interrupt, Haltproc
+  .set I2C1_ER_interrupt, Haltproc
+  .set I2C2_EV_interrupt, Haltproc
+  .set I2C2_ER_interrupt, Haltproc
+  .set SPI1_interrupt, Haltproc
+  .set SPI2_interrupt, Haltproc
+  .set USART1_interrupt, Haltproc
+  .set USART2_interrupt, Haltproc
+  .set USART3_interrupt, Haltproc
+  .set EXTI15_10_interrupt, Haltproc
+  .set RTC_Alarm_interrupt, Haltproc
+  .set USBWakeUp_interrupt, Haltproc
+  .set TIM8_BRK_interrupt, Haltproc
+  .set TIM8_UP_interrupt, Haltproc
+  .set TIM8_TRG_COM_interrupt, Haltproc
+  .set TIM8_CC_interrupt, Haltproc
+  .set ADC3_interrupt, Haltproc
+  .set FSMC_interrupt, Haltproc
+  .set SDIO_interrupt, Haltproc
+  .set TIM5_interrupt, Haltproc
+  .set SPI3_interrupt, Haltproc
+  .set UART4_interrupt, Haltproc
+  .set UART5_interrupt, Haltproc
+  .set TIM6_interrupt, Haltproc
+  .set TIM7_interrupt, Haltproc
+  .set DMA2_Channel1_interrupt, Haltproc
+  .set DMA2_Channel2_interrupt, Haltproc
+  .set DMA2_Channel3_interrupt, Haltproc
+  .set DMA2_Channel4_5_interrupt, Haltproc
+
+  .text
+  end;
+end.
diff --git a/rtl/freertos/arm/stm32f401xe.pp b/rtl/freertos/arm/stm32f401xe.pp
new file mode 100644
index 0000000000..a55da0b5ae
--- /dev/null
+++ b/rtl/freertos/arm/stm32f401xe.pp
@@ -0,0 +1,891 @@
+unit stm32f401xe;
+interface
+{$PACKRECORDS C}
+{$GOTO ON}
+{$SCOPEDENUMS ON}
+
+type
+  TIRQn_Enum = (
+    NonMaskableInt_IRQn = -14,        
+    MemoryManagement_IRQn = -12,      
+    BusFault_IRQn = -11,              
+    UsageFault_IRQn = -10,            
+    SVCall_IRQn = -5,                 
+    DebugMonitor_IRQn = -4,           
+    PendSV_IRQn = -2,                 
+    SysTick_IRQn = -1,                
+    WWDG_IRQn   = 0,                  
+    PVD_IRQn    = 1,                  
+    TAMP_STAMP_IRQn = 2,              
+    RTC_WKUP_IRQn = 3,                
+    FLASH_IRQn  = 4,                  
+    RCC_IRQn    = 5,                  
+    EXTI0_IRQn  = 6,                  
+    EXTI1_IRQn  = 7,                  
+    EXTI2_IRQn  = 8,                  
+    EXTI3_IRQn  = 9,                  
+    EXTI4_IRQn  = 10,                 
+    DMA1_Stream0_IRQn = 11,           
+    DMA1_Stream1_IRQn = 12,           
+    DMA1_Stream2_IRQn = 13,           
+    DMA1_Stream3_IRQn = 14,           
+    DMA1_Stream4_IRQn = 15,           
+    DMA1_Stream5_IRQn = 16,           
+    DMA1_Stream6_IRQn = 17,           
+    ADC_IRQn    = 18,                 
+    EXTI9_5_IRQn = 23,                
+    TIM1_BRK_TIM9_IRQn = 24,          
+    TIM1_UP_TIM10_IRQn = 25,          
+    TIM1_TRG_COM_TIM11_IRQn = 26,     
+    TIM1_CC_IRQn = 27,                
+    TIM2_IRQn   = 28,                 
+    TIM3_IRQn   = 29,                 
+    TIM4_IRQn   = 30,                 
+    I2C1_EV_IRQn = 31,                
+    I2C1_ER_IRQn = 32,                
+    I2C2_EV_IRQn = 33,                
+    I2C2_ER_IRQn = 34,                
+    SPI1_IRQn   = 35,                 
+    SPI2_IRQn   = 36,                 
+    USART1_IRQn = 37,                 
+    USART2_IRQn = 38,                 
+    EXTI15_10_IRQn = 40,              
+    RTC_Alarm_IRQn = 41,              
+    OTG_FS_WKUP_IRQn = 42,            
+    DMA1_Stream7_IRQn = 47,           
+    SDIO_IRQn   = 49,                 
+    TIM5_IRQn   = 50,                 
+    SPI3_IRQn   = 51,                 
+    DMA2_Stream0_IRQn = 56,           
+    DMA2_Stream1_IRQn = 57,           
+    DMA2_Stream2_IRQn = 58,           
+    DMA2_Stream3_IRQn = 59,           
+    DMA2_Stream4_IRQn = 60,           
+    OTG_FS_IRQn = 67,                 
+    DMA2_Stream5_IRQn = 68,           
+    DMA2_Stream6_IRQn = 69,           
+    DMA2_Stream7_IRQn = 70,           
+    USART6_IRQn = 71,                 
+    I2C3_EV_IRQn = 72,                
+    I2C3_ER_IRQn = 73,                
+    FPU_IRQn    = 81,                 
+    SPI4_IRQn   = 84                  
+  );
+
+  TADC_Registers = record
+    SR          : longword;
+    CR1         : longword;
+    CR2         : longword;
+    SMPR1       : longword;
+    SMPR2       : longword;
+    JOFR1       : longword;
+    JOFR2       : longword;
+    JOFR3       : longword;
+    JOFR4       : longword;
+    HTR         : longword;
+    LTR         : longword;
+    SQR1        : longword;
+    SQR2        : longword;
+    SQR3        : longword;
+    JSQR        : longword;
+    JDR1        : longword;
+    JDR2        : longword;
+    JDR3        : longword;
+    JDR4        : longword;
+    DR          : longword;
+  end;
+
+  TADC_Common_Registers = record
+    CSR         : longword;
+    CCR         : longword;
+    CDR         : longword;
+  end;
+
+  TCRC_Registers = record
+    DR          : longword;
+    IDR         : byte;
+    RESERVED0   : byte;
+    RESERVED1   : word;
+    CR          : longword;
+  end;
+
+  TDBGMCU_Registers = record
+    IDCODE      : longword;
+    CR          : longword;
+    APB1FZ      : longword;
+    APB2FZ      : longword;
+  end;
+
+  TDMA_Stream_Registers = record
+    CR          : longword;
+    NDTR        : longword;
+    PAR         : longword;
+    M0AR        : longword;
+    M1AR        : longword;
+    FCR         : longword;
+  end;
+
+  TDMA_Registers = record
+    LISR        : longword;
+    HISR        : longword;
+    LIFCR       : longword;
+    HIFCR       : longword;
+  end;
+
+  TEXTI_Registers = record
+    IMR         : longword;
+    EMR         : longword;
+    RTSR        : longword;
+    FTSR        : longword;
+    SWIER       : longword;
+    PR          : longword;
+  end;
+
+  TFLASH_Registers = record
+    ACR         : longword;
+    KEYR        : longword;
+    OPTKEYR     : longword;
+    SR          : longword;
+    CR          : longword;
+    OPTCR       : longword;
+    OPTCR1      : longword;
+  end;
+
+  TGPIO_Registers = record
+    MODER       : longword;
+    OTYPER      : longword;
+    OSPEEDR     : longword;
+    PUPDR       : longword;
+    IDR         : longword;
+    ODR         : longword;
+    BSRR        : longword;
+    LCKR        : longword;
+    AFR         : array[0..1] of longword;
+  end;
+
+  TSYSCFG_Registers = record
+    MEMRMP      : longword;
+    PMC         : longword;
+    EXTICR      : array[0..3] of longword;
+    RESERVED    : array[0..1] of longword;
+    CMPCR       : longword;
+  end;
+
+  TI2C_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    OAR1        : longword;
+    OAR2        : longword;
+    DR          : longword;
+    SR1         : longword;
+    SR2         : longword;
+    CCR         : longword;
+    TRISE       : longword;
+    FLTR        : longword;
+  end;
+
+  TIWDG_Registers = record
+    KR          : longword;
+    PR          : longword;
+    RLR         : longword;
+    SR          : longword;
+  end;
+
+  TPWR_Registers = record
+    CR          : longword;
+    CSR         : longword;
+  end;
+
+  TRCC_Registers = record
+    CR          : longword;
+    PLLCFGR     : longword;
+    CFGR        : longword;
+    CIR         : longword;
+    AHB1RSTR    : longword;
+    AHB2RSTR    : longword;
+    AHB3RSTR    : longword;
+    RESERVED0   : longword;
+    APB1RSTR    : longword;
+    APB2RSTR    : longword;
+    RESERVED1   : array[0..1] of longword;
+    AHB1ENR     : longword;
+    AHB2ENR     : longword;
+    AHB3ENR     : longword;
+    RESERVED2   : longword;
+    APB1ENR     : longword;
+    APB2ENR     : longword;
+    RESERVED3   : array[0..1] of longword;
+    AHB1LPENR   : longword;
+    AHB2LPENR   : longword;
+    AHB3LPENR   : longword;
+    RESERVED4   : longword;
+    APB1LPENR   : longword;
+    APB2LPENR   : longword;
+    RESERVED5   : array[0..1] of longword;
+    BDCR        : longword;
+    CSR         : longword;
+    RESERVED6   : array[0..1] of longword;
+    SSCGR       : longword;
+    PLLI2SCFGR  : longword;
+    RESERVED7   : longword;
+    DCKCFGR     : longword;
+  end;
+
+  TRTC_Registers = record
+    TR          : longword;
+    DR          : longword;
+    CR          : longword;
+    ISR         : longword;
+    PRER        : longword;
+    WUTR        : longword;
+    CALIBR      : longword;
+    ALRMAR      : longword;
+    ALRMBR      : longword;
+    WPR         : longword;
+    SSR         : longword;
+    SHIFTR      : longword;
+    TSTR        : longword;
+    TSDR        : longword;
+    TSSSR       : longword;
+    CALR        : longword;
+    TAFCR       : longword;
+    ALRMASSR    : longword;
+    ALRMBSSR    : longword;
+    RESERVED7   : longword;
+    BKP0R       : longword;
+    BKP1R       : longword;
+    BKP2R       : longword;
+    BKP3R       : longword;
+    BKP4R       : longword;
+    BKP5R       : longword;
+    BKP6R       : longword;
+    BKP7R       : longword;
+    BKP8R       : longword;
+    BKP9R       : longword;
+    BKP10R      : longword;
+    BKP11R      : longword;
+    BKP12R      : longword;
+    BKP13R      : longword;
+    BKP14R      : longword;
+    BKP15R      : longword;
+    BKP16R      : longword;
+    BKP17R      : longword;
+    BKP18R      : longword;
+    BKP19R      : longword;
+  end;
+
+  TSDIO_Registers = record
+    POWER       : longword;
+    CLKCR       : longword;
+    ARG         : longword;
+    CMD         : longword;
+    RESPCMD     : longword;
+    RESP1       : longword;
+    RESP2       : longword;
+    RESP3       : longword;
+    RESP4       : longword;
+    DTIMER      : longword;
+    DLEN        : longword;
+    DCTRL       : longword;
+    DCOUNT      : longword;
+    STA         : longword;
+    ICR         : longword;
+    MASK        : longword;
+    RESERVED0   : array[0..1] of longword;
+    FIFOCNT     : longword;
+    RESERVED1   : array[0..12] of longword;
+    FIFO        : longword;
+  end;
+
+  TSPI_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    SR          : longword;
+    DR          : longword;
+    CRCPR       : longword;
+    RXCRCR      : longword;
+    TXCRCR      : longword;
+    I2SCFGR     : longword;
+    I2SPR       : longword;
+  end;
+
+  TTIM_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    SMCR        : longword;
+    DIER        : longword;
+    SR          : longword;
+    EGR         : longword;
+    CCMR1       : longword;
+    CCMR2       : longword;
+    CCER        : longword;
+    CNT         : longword;
+    PSC         : longword;
+    ARR         : longword;
+    RCR         : longword;
+    CCR1        : longword;
+    CCR2        : longword;
+    CCR3        : longword;
+    CCR4        : longword;
+    BDTR        : longword;
+    DCR         : longword;
+    DMAR        : longword;
+    &OR         : longword;
+  end;
+
+  TUSART_Registers = record
+    SR          : longword;
+    DR          : longword;
+    BRR         : longword;
+    CR1         : longword;
+    CR2         : longword;
+    CR3         : longword;
+    GTPR        : longword;
+  end;
+
+  TWWDG_Registers = record
+    CR          : longword;
+    CFR         : longword;
+    SR          : longword;
+  end;
+
+  TUSB_OTG_Global_Registers = record
+    GOTGCTL     : longword;
+    GOTGINT     : longword;
+    GAHBCFG     : longword;
+    GUSBCFG     : longword;
+    GRSTCTL     : longword;
+    GINTSTS     : longword;
+    GINTMSK     : longword;
+    GRXSTSR     : longword;
+    GRXSTSP     : longword;
+    GRXFSIZ     : longword;
+    DIEPTXF0_HNPTXFSIZ : longword;
+    HNPTXSTS    : longword;
+    Reserved30  : array[0..1] of longword;
+    GCCFG       : longword;
+    CID         : longword;
+    Reserved40  : array[0..47] of longword;
+    HPTXFSIZ    : longword;
+    DIEPTXF     : array[0..14] of longword;
+  end;
+
+  TUSB_OTG_Device_Registers = record
+    DCFG        : longword;
+    DCTL        : longword;
+    DSTS        : longword;
+    Reserved0C  : longword;
+    DIEPMSK     : longword;
+    DOEPMSK     : longword;
+    DAINT       : longword;
+    DAINTMSK    : longword;
+    Reserved20  : longword;
+    Reserved9   : longword;
+    DVBUSDIS    : longword;
+    DVBUSPULSE  : longword;
+    DTHRCTL     : longword;
+    DIEPEMPMSK  : longword;
+    DEACHINT    : longword;
+    DEACHMSK    : longword;
+    Reserved40  : longword;
+    DINEP1MSK   : longword;
+    Reserved44  : array[0..14] of longword;
+    DOUTEP1MSK  : longword;
+  end;
+
+  TUSB_OTG_INEndpoint_Registers = record
+    DIEPCTL     : longword;
+    Reserved04  : longword;
+    DIEPINT     : longword;
+    Reserved0C  : longword;
+    DIEPTSIZ    : longword;
+    DIEPDMA     : longword;
+    DTXFSTS     : longword;
+    Reserved18  : longword;
+  end;
+
+  TUSB_OTG_OUTEndpoint_Registers = record
+    DOEPCTL     : longword;
+    Reserved04  : longword;
+    DOEPINT     : longword;
+    Reserved0C  : longword;
+    DOEPTSIZ    : longword;
+    DOEPDMA     : longword;
+    Reserved18  : array[0..1] of longword;
+  end;
+
+  TUSB_OTG_Host_Registers = record
+    HCFG        : longword;
+    HFIR        : longword;
+    HFNUM       : longword;
+    Reserved40C : longword;
+    HPTXSTS     : longword;
+    HAINT       : longword;
+    HAINTMSK    : longword;
+  end;
+
+  TUSB_OTG_HostChannel_Registers = record
+    HCCHAR      : longword;
+    HCSPLT      : longword;
+    HCINT       : longword;
+    HCINTMSK    : longword;
+    HCTSIZ      : longword;
+    HCDMA       : longword;
+    Reserved    : array[0..1] of longword;
+  end;
+
+const
+  FLASH_BASE    = $08000000;
+  SRAM1_BASE    = $20000000;
+  PERIPH_BASE   = $40000000;
+  SRAM1_BB_BASE = $22000000;
+  PERIPH_BB_BASE= $42000000;
+  BKPSRAM_BB_BASE= $42480000;
+  FLASH_OTP_BASE= $1FFF7800;
+  SRAM_BASE     = SRAM1_BASE;
+  SRAM_BB_BASE  = SRAM1_BB_BASE;
+  APB1PERIPH_BASE= PERIPH_BASE;
+  APB2PERIPH_BASE= PERIPH_BASE + $00010000;
+  AHB1PERIPH_BASE= PERIPH_BASE + $00020000;
+  AHB2PERIPH_BASE= PERIPH_BASE + $10000000;
+  TIM2_BASE     = APB1PERIPH_BASE + $0000;
+  TIM3_BASE     = APB1PERIPH_BASE + $0400;
+  TIM4_BASE     = APB1PERIPH_BASE + $0800;
+  TIM5_BASE     = APB1PERIPH_BASE + $0C00;
+  RTC_BASE      = APB1PERIPH_BASE + $2800;
+  WWDG_BASE     = APB1PERIPH_BASE + $2C00;
+  IWDG_BASE     = APB1PERIPH_BASE + $3000;
+  I2S2ext_BASE  = APB1PERIPH_BASE + $3400;
+  SPI2_BASE     = APB1PERIPH_BASE + $3800;
+  SPI3_BASE     = APB1PERIPH_BASE + $3C00;
+  I2S3ext_BASE  = APB1PERIPH_BASE + $4000;
+  USART2_BASE   = APB1PERIPH_BASE + $4400;
+  I2C1_BASE     = APB1PERIPH_BASE + $5400;
+  I2C2_BASE     = APB1PERIPH_BASE + $5800;
+  I2C3_BASE     = APB1PERIPH_BASE + $5C00;
+  PWR_BASE      = APB1PERIPH_BASE + $7000;
+  TIM1_BASE     = APB2PERIPH_BASE + $0000;
+  USART1_BASE   = APB2PERIPH_BASE + $1000;
+  USART6_BASE   = APB2PERIPH_BASE + $1400;
+  ADC1_BASE     = APB2PERIPH_BASE + $2000;
+  ADC1_COMMON_BASE= APB2PERIPH_BASE + $2300;
+  ADC_BASE      = ADC1_COMMON_BASE;
+  SDIO_BASE     = APB2PERIPH_BASE + $2C00;
+  SPI1_BASE     = APB2PERIPH_BASE + $3000;
+  SPI4_BASE     = APB2PERIPH_BASE + $3400;
+  SYSCFG_BASE   = APB2PERIPH_BASE + $3800;
+  EXTI_BASE     = APB2PERIPH_BASE + $3C00;
+  TIM9_BASE     = APB2PERIPH_BASE + $4000;
+  TIM10_BASE    = APB2PERIPH_BASE + $4400;
+  TIM11_BASE    = APB2PERIPH_BASE + $4800;
+  GPIOA_BASE    = AHB1PERIPH_BASE + $0000;
+  GPIOB_BASE    = AHB1PERIPH_BASE + $0400;
+  GPIOC_BASE    = AHB1PERIPH_BASE + $0800;
+  GPIOD_BASE    = AHB1PERIPH_BASE + $0C00;
+  GPIOE_BASE    = AHB1PERIPH_BASE + $1000;
+  GPIOH_BASE    = AHB1PERIPH_BASE + $1C00;
+  CRC_BASE      = AHB1PERIPH_BASE + $3000;
+  RCC_BASE      = AHB1PERIPH_BASE + $3800;
+  FLASH_R_BASE  = AHB1PERIPH_BASE + $3C00;
+  DMA1_BASE     = AHB1PERIPH_BASE + $6000;
+  DMA1_Stream0_BASE= DMA1_BASE + $010;
+  DMA1_Stream1_BASE= DMA1_BASE + $028;
+  DMA1_Stream2_BASE= DMA1_BASE + $040;
+  DMA1_Stream3_BASE= DMA1_BASE + $058;
+  DMA1_Stream4_BASE= DMA1_BASE + $070;
+  DMA1_Stream5_BASE= DMA1_BASE + $088;
+  DMA1_Stream6_BASE= DMA1_BASE + $0A0;
+  DMA1_Stream7_BASE= DMA1_BASE + $0B8;
+  DMA2_BASE     = AHB1PERIPH_BASE + $6400;
+  DMA2_Stream0_BASE= DMA2_BASE + $010;
+  DMA2_Stream1_BASE= DMA2_BASE + $028;
+  DMA2_Stream2_BASE= DMA2_BASE + $040;
+  DMA2_Stream3_BASE= DMA2_BASE + $058;
+  DMA2_Stream4_BASE= DMA2_BASE + $070;
+  DMA2_Stream5_BASE= DMA2_BASE + $088;
+  DMA2_Stream6_BASE= DMA2_BASE + $0A0;
+  DMA2_Stream7_BASE= DMA2_BASE + $0B8;
+  DBGMCU_BASE   = $E0042000;
+  USB_OTG_FS_PERIPH_BASE= $50000000;
+  USB_OTG_GLOBAL_BASE= $000;
+  USB_OTG_DEVICE_BASE= $800;
+  USB_OTG_IN_ENDPOINT_BASE= $900;
+  USB_OTG_OUT_ENDPOINT_BASE= $B00;
+  USB_OTG_HOST_BASE= $400;
+  USB_OTG_HOST_PORT_BASE= $440;
+  USB_OTG_HOST_CHANNEL_BASE= $500;
+  USB_OTG_PCGCCTL_BASE= $E00;
+  USB_OTG_FIFO_BASE= $1000;
+  UID_BASE      = $1FFF7A10;
+  FLASHSIZE_BASE= $1FFF7A22;
+  PACKAGE_BASE  = $1FFF7BF0;
+
+var
+  TIM2          : TTIM_Registers absolute TIM2_BASE;
+  TIM3          : TTIM_Registers absolute TIM3_BASE;
+  TIM4          : TTIM_Registers absolute TIM4_BASE;
+  TIM5          : TTIM_Registers absolute TIM5_BASE;
+  RTC           : TRTC_Registers absolute RTC_BASE;
+  WWDG          : TWWDG_Registers absolute WWDG_BASE;
+  IWDG          : TIWDG_Registers absolute IWDG_BASE;
+  I2S2ext       : TSPI_Registers absolute I2S2ext_BASE;
+  SPI2          : TSPI_Registers absolute SPI2_BASE;
+  SPI3          : TSPI_Registers absolute SPI3_BASE;
+  I2S3ext       : TSPI_Registers absolute I2S3ext_BASE;
+  USART2        : TUSART_Registers absolute USART2_BASE;
+  I2C1          : TI2C_Registers absolute I2C1_BASE;
+  I2C2          : TI2C_Registers absolute I2C2_BASE;
+  I2C3          : TI2C_Registers absolute I2C3_BASE;
+  PWR           : TPWR_Registers absolute PWR_BASE;
+  TIM1          : TTIM_Registers absolute TIM1_BASE;
+  USART1        : TUSART_Registers absolute USART1_BASE;
+  USART6        : TUSART_Registers absolute USART6_BASE;
+  ADC1          : TADC_Registers absolute ADC1_BASE;
+  ADC1_COMMON   : TADC_Common_Registers absolute ADC1_COMMON_BASE;
+  SDIO          : TSDIO_Registers absolute SDIO_BASE;
+  SPI1          : TSPI_Registers absolute SPI1_BASE;
+  SPI4          : TSPI_Registers absolute SPI4_BASE;
+  SYSCFG        : TSYSCFG_Registers absolute SYSCFG_BASE;
+  EXTI          : TEXTI_Registers absolute EXTI_BASE;
+  TIM9          : TTIM_Registers absolute TIM9_BASE;
+  TIM10         : TTIM_Registers absolute TIM10_BASE;
+  TIM11         : TTIM_Registers absolute TIM11_BASE;
+  GPIOA         : TGPIO_Registers absolute GPIOA_BASE;
+  GPIOB         : TGPIO_Registers absolute GPIOB_BASE;
+  GPIOC         : TGPIO_Registers absolute GPIOC_BASE;
+  GPIOD         : TGPIO_Registers absolute GPIOD_BASE;
+  GPIOE         : TGPIO_Registers absolute GPIOE_BASE;
+  GPIOH         : TGPIO_Registers absolute GPIOH_BASE;
+  CRC           : TCRC_Registers absolute CRC_BASE;
+  RCC           : TRCC_Registers absolute RCC_BASE;
+  FLASH         : TFLASH_Registers absolute FLASH_R_BASE;
+  DMA1          : TDMA_Registers absolute DMA1_BASE;
+  DMA1_Stream0  : TDMA_Stream_Registers absolute DMA1_Stream0_BASE;
+  DMA1_Stream1  : TDMA_Stream_Registers absolute DMA1_Stream1_BASE;
+  DMA1_Stream2  : TDMA_Stream_Registers absolute DMA1_Stream2_BASE;
+  DMA1_Stream3  : TDMA_Stream_Registers absolute DMA1_Stream3_BASE;
+  DMA1_Stream4  : TDMA_Stream_Registers absolute DMA1_Stream4_BASE;
+  DMA1_Stream5  : TDMA_Stream_Registers absolute DMA1_Stream5_BASE;
+  DMA1_Stream6  : TDMA_Stream_Registers absolute DMA1_Stream6_BASE;
+  DMA1_Stream7  : TDMA_Stream_Registers absolute DMA1_Stream7_BASE;
+  DMA2          : TDMA_Registers absolute DMA2_BASE;
+  DMA2_Stream0  : TDMA_Stream_Registers absolute DMA2_Stream0_BASE;
+  DMA2_Stream1  : TDMA_Stream_Registers absolute DMA2_Stream1_BASE;
+  DMA2_Stream2  : TDMA_Stream_Registers absolute DMA2_Stream2_BASE;
+  DMA2_Stream3  : TDMA_Stream_Registers absolute DMA2_Stream3_BASE;
+  DMA2_Stream4  : TDMA_Stream_Registers absolute DMA2_Stream4_BASE;
+  DMA2_Stream5  : TDMA_Stream_Registers absolute DMA2_Stream5_BASE;
+  DMA2_Stream6  : TDMA_Stream_Registers absolute DMA2_Stream6_BASE;
+  DMA2_Stream7  : TDMA_Stream_Registers absolute DMA2_Stream7_BASE;
+  DBGMCU        : TDBGMCU_Registers absolute DBGMCU_BASE;
+
+implementation
+
+procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
+procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SVCall_interrupt; external name 'SVCall_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendSV_interrupt; external name 'PendSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure WWDG_interrupt; external name 'WWDG_interrupt';
+procedure PVD_interrupt; external name 'PVD_interrupt';
+procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt';
+procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt';
+procedure FLASH_interrupt; external name 'FLASH_interrupt';
+procedure RCC_interrupt; external name 'RCC_interrupt';
+procedure EXTI0_interrupt; external name 'EXTI0_interrupt';
+procedure EXTI1_interrupt; external name 'EXTI1_interrupt';
+procedure EXTI2_interrupt; external name 'EXTI2_interrupt';
+procedure EXTI3_interrupt; external name 'EXTI3_interrupt';
+procedure EXTI4_interrupt; external name 'EXTI4_interrupt';
+procedure DMA1_Stream0_interrupt; external name 'DMA1_Stream0_interrupt';
+procedure DMA1_Stream1_interrupt; external name 'DMA1_Stream1_interrupt';
+procedure DMA1_Stream2_interrupt; external name 'DMA1_Stream2_interrupt';
+procedure DMA1_Stream3_interrupt; external name 'DMA1_Stream3_interrupt';
+procedure DMA1_Stream4_interrupt; external name 'DMA1_Stream4_interrupt';
+procedure DMA1_Stream5_interrupt; external name 'DMA1_Stream5_interrupt';
+procedure DMA1_Stream6_interrupt; external name 'DMA1_Stream6_interrupt';
+procedure ADC_interrupt; external name 'ADC_interrupt';
+procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt';
+procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt';
+procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt';
+procedure TIM1_TRG_COM_TIM11_interrupt; external name 'TIM1_TRG_COM_TIM11_interrupt';
+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
+procedure TIM2_interrupt; external name 'TIM2_interrupt';
+procedure TIM3_interrupt; external name 'TIM3_interrupt';
+procedure TIM4_interrupt; external name 'TIM4_interrupt';
+procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt';
+procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt';
+procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt';
+procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt';
+procedure SPI1_interrupt; external name 'SPI1_interrupt';
+procedure SPI2_interrupt; external name 'SPI2_interrupt';
+procedure USART1_interrupt; external name 'USART1_interrupt';
+procedure USART2_interrupt; external name 'USART2_interrupt';
+procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt';
+procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt';
+procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt';
+procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt';
+procedure SDIO_interrupt; external name 'SDIO_interrupt';
+procedure TIM5_interrupt; external name 'TIM5_interrupt';
+procedure SPI3_interrupt; external name 'SPI3_interrupt';
+procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt';
+procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt';
+procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt';
+procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt';
+procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt';
+procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt';
+procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt';
+procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt';
+procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt';
+procedure USART6_interrupt; external name 'USART6_interrupt';
+procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt';
+procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt';
+procedure FPU_interrupt; external name 'FPU_interrupt';
+procedure SPI4_interrupt; external name 'SPI4_interrupt';
+
+
+{$i cortexm4f_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+  .section ".init.interrupt_vectors"
+  interrupt_vectors:
+  .long _stack_top
+  .long Startup
+  .long NonMaskableInt_interrupt
+  .long 0
+  .long MemoryManagement_interrupt
+  .long BusFault_interrupt
+  .long UsageFault_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long SVCall_interrupt
+  .long DebugMonitor_interrupt
+  .long 0
+  .long PendSV_interrupt
+  .long SysTick_interrupt
+  .long WWDG_interrupt
+  .long PVD_interrupt
+  .long TAMP_STAMP_interrupt
+  .long RTC_WKUP_interrupt
+  .long FLASH_interrupt
+  .long RCC_interrupt
+  .long EXTI0_interrupt
+  .long EXTI1_interrupt
+  .long EXTI2_interrupt
+  .long EXTI3_interrupt
+  .long EXTI4_interrupt
+  .long DMA1_Stream0_interrupt
+  .long DMA1_Stream1_interrupt
+  .long DMA1_Stream2_interrupt
+  .long DMA1_Stream3_interrupt
+  .long DMA1_Stream4_interrupt
+  .long DMA1_Stream5_interrupt
+  .long DMA1_Stream6_interrupt
+  .long ADC_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long EXTI9_5_interrupt
+  .long TIM1_BRK_TIM9_interrupt
+  .long TIM1_UP_TIM10_interrupt
+  .long TIM1_TRG_COM_TIM11_interrupt
+  .long TIM1_CC_interrupt
+  .long TIM2_interrupt
+  .long TIM3_interrupt
+  .long TIM4_interrupt
+  .long I2C1_EV_interrupt
+  .long I2C1_ER_interrupt
+  .long I2C2_EV_interrupt
+  .long I2C2_ER_interrupt
+  .long SPI1_interrupt
+  .long SPI2_interrupt
+  .long USART1_interrupt
+  .long USART2_interrupt
+  .long 0
+  .long EXTI15_10_interrupt
+  .long RTC_Alarm_interrupt
+  .long OTG_FS_WKUP_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long DMA1_Stream7_interrupt
+  .long 0
+  .long SDIO_interrupt
+  .long TIM5_interrupt
+  .long SPI3_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long DMA2_Stream0_interrupt
+  .long DMA2_Stream1_interrupt
+  .long DMA2_Stream2_interrupt
+  .long DMA2_Stream3_interrupt
+  .long DMA2_Stream4_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long OTG_FS_interrupt
+  .long DMA2_Stream5_interrupt
+  .long DMA2_Stream6_interrupt
+  .long DMA2_Stream7_interrupt
+  .long USART6_interrupt
+  .long I2C3_EV_interrupt
+  .long I2C3_ER_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long FPU_interrupt
+  .long 0
+  .long 0
+  .long SPI4_interrupt
+
+  .weak NonMaskableInt_interrupt
+  .weak MemoryManagement_interrupt
+  .weak BusFault_interrupt
+  .weak UsageFault_interrupt
+  .weak SVCall_interrupt
+  .weak DebugMonitor_interrupt
+  .weak PendSV_interrupt
+  .weak SysTick_interrupt
+  .weak WWDG_interrupt
+  .weak PVD_interrupt
+  .weak TAMP_STAMP_interrupt
+  .weak RTC_WKUP_interrupt
+  .weak FLASH_interrupt
+  .weak RCC_interrupt
+  .weak EXTI0_interrupt
+  .weak EXTI1_interrupt
+  .weak EXTI2_interrupt
+  .weak EXTI3_interrupt
+  .weak EXTI4_interrupt
+  .weak DMA1_Stream0_interrupt
+  .weak DMA1_Stream1_interrupt
+  .weak DMA1_Stream2_interrupt
+  .weak DMA1_Stream3_interrupt
+  .weak DMA1_Stream4_interrupt
+  .weak DMA1_Stream5_interrupt
+  .weak DMA1_Stream6_interrupt
+  .weak ADC_interrupt
+  .weak EXTI9_5_interrupt
+  .weak TIM1_BRK_TIM9_interrupt
+  .weak TIM1_UP_TIM10_interrupt
+  .weak TIM1_TRG_COM_TIM11_interrupt
+  .weak TIM1_CC_interrupt
+  .weak TIM2_interrupt
+  .weak TIM3_interrupt
+  .weak TIM4_interrupt
+  .weak I2C1_EV_interrupt
+  .weak I2C1_ER_interrupt
+  .weak I2C2_EV_interrupt
+  .weak I2C2_ER_interrupt
+  .weak SPI1_interrupt
+  .weak SPI2_interrupt
+  .weak USART1_interrupt
+  .weak USART2_interrupt
+  .weak EXTI15_10_interrupt
+  .weak RTC_Alarm_interrupt
+  .weak OTG_FS_WKUP_interrupt
+  .weak DMA1_Stream7_interrupt
+  .weak SDIO_interrupt
+  .weak TIM5_interrupt
+  .weak SPI3_interrupt
+  .weak DMA2_Stream0_interrupt
+  .weak DMA2_Stream1_interrupt
+  .weak DMA2_Stream2_interrupt
+  .weak DMA2_Stream3_interrupt
+  .weak DMA2_Stream4_interrupt
+  .weak OTG_FS_interrupt
+  .weak DMA2_Stream5_interrupt
+  .weak DMA2_Stream6_interrupt
+  .weak DMA2_Stream7_interrupt
+  .weak USART6_interrupt
+  .weak I2C3_EV_interrupt
+  .weak I2C3_ER_interrupt
+  .weak FPU_interrupt
+  .weak SPI4_interrupt
+
+  .set NonMaskableInt_interrupt, Haltproc
+  .set MemoryManagement_interrupt, Haltproc
+  .set BusFault_interrupt, Haltproc
+  .set UsageFault_interrupt, Haltproc
+  .set SVCall_interrupt, Haltproc
+  .set DebugMonitor_interrupt, Haltproc
+  .set PendSV_interrupt, Haltproc
+  .set SysTick_interrupt, Haltproc
+  .set WWDG_interrupt, Haltproc
+  .set PVD_interrupt, Haltproc
+  .set TAMP_STAMP_interrupt, Haltproc
+  .set RTC_WKUP_interrupt, Haltproc
+  .set FLASH_interrupt, Haltproc
+  .set RCC_interrupt, Haltproc
+  .set EXTI0_interrupt, Haltproc
+  .set EXTI1_interrupt, Haltproc
+  .set EXTI2_interrupt, Haltproc
+  .set EXTI3_interrupt, Haltproc
+  .set EXTI4_interrupt, Haltproc
+  .set DMA1_Stream0_interrupt, Haltproc
+  .set DMA1_Stream1_interrupt, Haltproc
+  .set DMA1_Stream2_interrupt, Haltproc
+  .set DMA1_Stream3_interrupt, Haltproc
+  .set DMA1_Stream4_interrupt, Haltproc
+  .set DMA1_Stream5_interrupt, Haltproc
+  .set DMA1_Stream6_interrupt, Haltproc
+  .set ADC_interrupt, Haltproc
+  .set EXTI9_5_interrupt, Haltproc
+  .set TIM1_BRK_TIM9_interrupt, Haltproc
+  .set TIM1_UP_TIM10_interrupt, Haltproc
+  .set TIM1_TRG_COM_TIM11_interrupt, Haltproc
+  .set TIM1_CC_interrupt, Haltproc
+  .set TIM2_interrupt, Haltproc
+  .set TIM3_interrupt, Haltproc
+  .set TIM4_interrupt, Haltproc
+  .set I2C1_EV_interrupt, Haltproc
+  .set I2C1_ER_interrupt, Haltproc
+  .set I2C2_EV_interrupt, Haltproc
+  .set I2C2_ER_interrupt, Haltproc
+  .set SPI1_interrupt, Haltproc
+  .set SPI2_interrupt, Haltproc
+  .set USART1_interrupt, Haltproc
+  .set USART2_interrupt, Haltproc
+  .set EXTI15_10_interrupt, Haltproc
+  .set RTC_Alarm_interrupt, Haltproc
+  .set OTG_FS_WKUP_interrupt, Haltproc
+  .set DMA1_Stream7_interrupt, Haltproc
+  .set SDIO_interrupt, Haltproc
+  .set TIM5_interrupt, Haltproc
+  .set SPI3_interrupt, Haltproc
+  .set DMA2_Stream0_interrupt, Haltproc
+  .set DMA2_Stream1_interrupt, Haltproc
+  .set DMA2_Stream2_interrupt, Haltproc
+  .set DMA2_Stream3_interrupt, Haltproc
+  .set DMA2_Stream4_interrupt, Haltproc
+  .set OTG_FS_interrupt, Haltproc
+  .set DMA2_Stream5_interrupt, Haltproc
+  .set DMA2_Stream6_interrupt, Haltproc
+  .set DMA2_Stream7_interrupt, Haltproc
+  .set USART6_interrupt, Haltproc
+  .set I2C3_EV_interrupt, Haltproc
+  .set I2C3_ER_interrupt, Haltproc
+  .set FPU_interrupt, Haltproc
+  .set SPI4_interrupt, Haltproc
+
+  .text
+  end;
+end.
diff --git a/rtl/freertos/arm/stm32g071xx.pp b/rtl/freertos/arm/stm32g071xx.pp
new file mode 100644
index 0000000000..68d3839b92
--- /dev/null
+++ b/rtl/freertos/arm/stm32g071xx.pp
@@ -0,0 +1,760 @@
+unit stm32g071xx;
+interface
+{$PACKRECORDS C}
+{$GOTO ON}
+{$SCOPEDENUMS ON}
+
+type
+  TIRQn_Enum = (
+    NonMaskableInt_IRQn = -14,        
+    HardFault_IRQn = -13,             
+    SVC_IRQn    = -5,                 
+    PendSV_IRQn = -2,                 
+    SysTick_IRQn = -1,                
+    WWDG_IRQn   = 0,                  
+    PVD_IRQn    = 1,                  
+    RTC_TAMP_IRQn = 2,                
+    FLASH_IRQn  = 3,                  
+    RCC_IRQn    = 4,                  
+    EXTI0_1_IRQn = 5,                 
+    EXTI2_3_IRQn = 6,                 
+    EXTI4_15_IRQn = 7,                
+    UCPD1_2_IRQn = 8,                 
+    DMA1_Channel1_IRQn = 9,           
+    DMA1_Channel2_3_IRQn = 10,        
+    DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, 
+    ADC1_COMP_IRQn = 12,              
+    TIM1_BRK_UP_TRG_COM_IRQn = 13,    
+    TIM1_CC_IRQn = 14,                
+    TIM2_IRQn   = 15,                 
+    TIM3_IRQn   = 16,                 
+    TIM6_DAC_LPTIM1_IRQn = 17,        
+    TIM7_LPTIM2_IRQn = 18,            
+    TIM14_IRQn  = 19,                 
+    TIM15_IRQn  = 20,                 
+    TIM16_IRQn  = 21,                 
+    TIM17_IRQn  = 22,                 
+    I2C1_IRQn   = 23,                 
+    I2C2_IRQn   = 24,                 
+    SPI1_IRQn   = 25,                 
+    SPI2_IRQn   = 26,                 
+    USART1_IRQn = 27,                 
+    USART2_IRQn = 28,                 
+    USART3_4_LPUART1_IRQn = 29,       
+    CEC_IRQn    = 30                  
+  );
+
+  TADC_Registers = record
+    ISR         : longword;
+    IER         : longword;
+    CR          : longword;
+    CFGR1       : longword;
+    CFGR2       : longword;
+    SMPR        : longword;
+    RESERVED1   : longword;
+    RESERVED2   : longword;
+    TR1         : longword;
+    TR2         : longword;
+    CHSELR      : longword;
+    TR3         : longword;
+    RESERVED3   : array[0..3] of longword;
+    DR          : longword;
+    RESERVED4   : array[0..22] of longword;
+    AWD2CR      : longword;
+    AWD3CR      : longword;
+    RESERVED5   : array[0..2] of longword;
+    CALFACT     : longword;
+  end;
+
+  TADC_Common_Registers = record
+    CCR         : longword;
+  end;
+
+  TCEC_Registers = record
+    CR          : longword;
+    CFGR        : longword;
+    TXDR        : longword;
+    RXDR        : longword;
+    ISR         : longword;
+    IER         : longword;
+  end;
+
+  TCOMP_Registers = record
+    CSR         : longword;
+  end;
+
+  TCOMP_Common_Registers = record
+    CSR_ODD     : longword;
+    CSR_EVEN    : longword;
+  end;
+
+  TCRC_Registers = record
+    DR          : longword;
+    IDR         : longword;
+    CR          : longword;
+    RESERVED1   : longword;
+    INIT        : longword;
+    POL         : longword;
+  end;
+
+  TDAC_Registers = record
+    CR          : longword;
+    SWTRIGR     : longword;
+    DHR12R1     : longword;
+    DHR12L1     : longword;
+    DHR8R1      : longword;
+    DHR12R2     : longword;
+    DHR12L2     : longword;
+    DHR8R2      : longword;
+    DHR12RD     : longword;
+    DHR12LD     : longword;
+    DHR8RD      : longword;
+    DOR1        : longword;
+    DOR2        : longword;
+    SR          : longword;
+    CCR         : longword;
+    MCR         : longword;
+    SHSR1       : longword;
+    SHSR2       : longword;
+    SHHR        : longword;
+    SHRR        : longword;
+  end;
+
+  TDBG_Registers = record
+    IDCODE      : longword;
+    CR          : longword;
+    APBFZ1      : longword;
+    APBFZ2      : longword;
+  end;
+
+  TDMA_Channel_Registers = record
+    CCR         : longword;
+    CNDTR       : longword;
+    CPAR        : longword;
+    CMAR        : longword;
+  end;
+
+  TDMA_Registers = record
+    ISR         : longword;
+    IFCR        : longword;
+  end;
+
+  TDMAMUX_Channel_Registers = record
+    CCR         : longword;
+  end;
+
+  TDMAMUX_ChannelStatus_Registers = record
+    CSR         : longword;
+    CFR         : longword;
+  end;
+
+  TDMAMUX_RequestGen_Registers = record
+    RGCR        : longword;
+  end;
+
+  TDMAMUX_RequestGenStatus_Registers = record
+    RGSR        : longword;
+    RGCFR       : longword;
+  end;
+
+  TEXTI_Registers = record
+    RTSR1       : longword;
+    FTSR1       : longword;
+    SWIER1      : longword;
+    RPR1        : longword;
+    FPR1        : longword;
+    RESERVED1   : array[0..2] of longword;
+    RESERVED2   : array[0..4] of longword;
+    RESERVED3   : array[0..10] of longword;
+    EXTICR      : array[0..3] of longword;
+    RESERVED4   : array[0..3] of longword;
+    IMR1        : longword;
+    EMR1        : longword;
+    RESERVED5   : array[0..1] of longword;
+    IMR2        : longword;
+    EMR2        : longword;
+  end;
+
+  TFLASH_Registers = record
+    ACR         : longword;
+    RESERVED1   : longword;
+    KEYR        : longword;
+    OPTKEYR     : longword;
+    SR          : longword;
+    CR          : longword;
+    ECCR        : longword;
+    RESERVED2   : longword;
+    OPTR        : longword;
+    PCROP1ASR   : longword;
+    PCROP1AER   : longword;
+    WRP1AR      : longword;
+    WRP1BR      : longword;
+    PCROP1BSR   : longword;
+    PCROP1BER   : longword;
+    RESERVED3   : array[0..16] of longword;
+    SECR        : longword;
+  end;
+
+  TGPIO_Registers = record
+    MODER       : longword;
+    OTYPER      : longword;
+    OSPEEDR     : longword;
+    PUPDR       : longword;
+    IDR         : longword;
+    ODR         : longword;
+    BSRR        : longword;
+    LCKR        : longword;
+    AFR         : array[0..1] of longword;
+    BRR         : longword;
+  end;
+
+  TI2C_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    OAR1        : longword;
+    OAR2        : longword;
+    TIMINGR     : longword;
+    TIMEOUTR    : longword;
+    ISR         : longword;
+    ICR         : longword;
+    PECR        : longword;
+    RXDR        : longword;
+    TXDR        : longword;
+  end;
+
+  TIWDG_Registers = record
+    KR          : longword;
+    PR          : longword;
+    RLR         : longword;
+    SR          : longword;
+    WINR        : longword;
+  end;
+
+  TLPTIM_Registers = record
+    ISR         : longword;
+    ICR         : longword;
+    IER         : longword;
+    CFGR        : longword;
+    CR          : longword;
+    CMP         : longword;
+    ARR         : longword;
+    CNT         : longword;
+    RESERVED1   : longword;
+    CFGR2       : longword;
+  end;
+
+  TPWR_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    CR3         : longword;
+    CR4         : longword;
+    SR1         : longword;
+    SR2         : longword;
+    SCR         : longword;
+    RESERVED1   : longword;
+    PUCRA       : longword;
+    PDCRA       : longword;
+    PUCRB       : longword;
+    PDCRB       : longword;
+    PUCRC       : longword;
+    PDCRC       : longword;
+    PUCRD       : longword;
+    PDCRD       : longword;
+    RESERVED2   : longword;
+    RESERVED3   : longword;
+    PUCRF       : longword;
+    PDCRF       : longword;
+  end;
+
+  TRCC_Registers = record
+    CR          : longword;
+    ICSCR       : longword;
+    CFGR        : longword;
+    PLLCFGR     : longword;
+    RESERVED0   : longword;
+    RESERVED1   : longword;
+    CIER        : longword;
+    CIFR        : longword;
+    CICR        : longword;
+    IOPRSTR     : longword;
+    AHBRSTR     : longword;
+    APBRSTR1    : longword;
+    APBRSTR2    : longword;
+    IOPENR      : longword;
+    AHBENR      : longword;
+    APBENR1     : longword;
+    APBENR2     : longword;
+    IOPSMENR    : longword;
+    AHBSMENR    : longword;
+    APBSMENR1   : longword;
+    APBSMENR2   : longword;
+    CCIPR       : longword;
+    RESERVED2   : longword;
+    BDCR        : longword;
+    CSR         : longword;
+  end;
+
+  TRTC_Registers = record
+    TR          : longword;
+    DR          : longword;
+    SSR         : longword;
+    ICSR        : longword;
+    PRER        : longword;
+    WUTR        : longword;
+    CR          : longword;
+    RESERVED0   : longword;
+    RESERVED1   : longword;
+    WPR         : longword;
+    CALR        : longword;
+    SHIFTR      : longword;
+    TSTR        : longword;
+    TSDR        : longword;
+    TSSSR       : longword;
+    RESERVED2   : longword;
+    ALRMAR      : longword;
+    ALRMASSR    : longword;
+    ALRMBR      : longword;
+    ALRMBSSR    : longword;
+    SR          : longword;
+    MISR        : longword;
+    RESERVED3   : longword;
+    SCR         : longword;
+    &OR         : longword;
+  end;
+
+  TTAMP_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    RESERVED0   : longword;
+    FLTCR       : longword;
+    RESERVED1   : array[0..6] of longword;
+    IER         : longword;
+    SR          : longword;
+    MISR        : longword;
+    RESERVED2   : longword;
+    SCR         : longword;
+    RESERVED3   : array[0..47] of longword;
+    BKP0R       : longword;
+    BKP1R       : longword;
+    BKP2R       : longword;
+    BKP3R       : longword;
+    BKP4R       : longword;
+  end;
+
+  TSPI_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    SR          : longword;
+    DR          : longword;
+    CRCPR       : longword;
+    RXCRCR      : longword;
+    TXCRCR      : longword;
+    I2SCFGR     : longword;
+    I2SPR       : longword;
+  end;
+
+  TSYSCFG_Registers = record
+    CFGR1       : longword;
+    RESERVED0   : array[0..4] of longword;
+    CFGR2       : longword;
+    RESERVED1   : array[0..24] of longword;
+    IT_LINE_SR  : array[0..31] of longword;
+  end;
+
+  TTIM_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    SMCR        : longword;
+    DIER        : longword;
+    SR          : longword;
+    EGR         : longword;
+    CCMR1       : longword;
+    CCMR2       : longword;
+    CCER        : longword;
+    CNT         : longword;
+    PSC         : longword;
+    ARR         : longword;
+    RCR         : longword;
+    CCR1        : longword;
+    CCR2        : longword;
+    CCR3        : longword;
+    CCR4        : longword;
+    BDTR        : longword;
+    DCR         : longword;
+    DMAR        : longword;
+    OR1         : longword;
+    CCMR3       : longword;
+    CCR5        : longword;
+    CCR6        : longword;
+    AF1         : longword;
+    AF2         : longword;
+    TISEL       : longword;
+  end;
+
+  TUSART_Registers = record
+    CR1         : longword;
+    CR2         : longword;
+    CR3         : longword;
+    BRR         : longword;
+    GTPR        : longword;
+    RTOR        : longword;
+    RQR         : longword;
+    ISR         : longword;
+    ICR         : longword;
+    RDR         : longword;
+    TDR         : longword;
+    PRESC       : longword;
+  end;
+
+  TVREFBUF_Registers = record
+    CSR         : longword;
+    CCR         : longword;
+  end;
+
+  TWWDG_Registers = record
+    CR          : longword;
+    CFR         : longword;
+    SR          : longword;
+  end;
+
+  TUCPD_Registers = record
+    CFG1        : longword;
+    CFG2        : longword;
+    RESERVED0   : longword;
+    CR          : longword;
+    IMR         : longword;
+    SR          : longword;
+    ICR         : longword;
+    TX_ORDSET   : longword;
+    TX_PAYSZ    : longword;
+    TXDR        : longword;
+    RX_ORDSET   : longword;
+    RX_PAYSZ    : longword;
+    RXDR        : longword;
+    RX_ORDEXT1  : longword;
+    RX_ORDEXT2  : longword;
+  end;
+
+const
+  FLASH_BASE    = $08000000;
+  SRAM_BASE     = $20000000;
+  PERIPH_BASE   = $40000000;
+  IOPORT_BASE   = $50000000;
+  APBPERIPH_BASE= PERIPH_BASE;
+  AHBPERIPH_BASE= PERIPH_BASE + $00020000;
+  TIM2_BASE     = APBPERIPH_BASE + 0;
+  TIM3_BASE     = APBPERIPH_BASE + $00000400;
+  TIM6_BASE     = APBPERIPH_BASE + $00001000;
+  TIM7_BASE     = APBPERIPH_BASE + $00001400;
+  TIM14_BASE    = APBPERIPH_BASE + $00002000;
+  RTC_BASE      = APBPERIPH_BASE + $00002800;
+  WWDG_BASE     = APBPERIPH_BASE + $00002C00;
+  IWDG_BASE     = APBPERIPH_BASE + $00003000;
+  SPI2_BASE     = APBPERIPH_BASE + $00003800;
+  USART2_BASE   = APBPERIPH_BASE + $00004400;
+  USART3_BASE   = APBPERIPH_BASE + $00004800;
+  USART4_BASE   = APBPERIPH_BASE + $00004C00;
+  I2C1_BASE     = APBPERIPH_BASE + $00005400;
+  I2C2_BASE     = APBPERIPH_BASE + $00005800;
+  PWR_BASE      = APBPERIPH_BASE + $00007000;
+  DAC1_BASE     = APBPERIPH_BASE + $00007400;
+  DAC_BASE      = APBPERIPH_BASE + $00007400;
+  CEC_BASE      = APBPERIPH_BASE + $00007800;
+  LPTIM1_BASE   = APBPERIPH_BASE + $00007C00;
+  LPUART1_BASE  = APBPERIPH_BASE + $00008000;
+  LPTIM2_BASE   = APBPERIPH_BASE + $00009400;
+  UCPD1_BASE    = APBPERIPH_BASE + $0000A000;
+  UCPD2_BASE    = APBPERIPH_BASE + $0000A400;
+  TAMP_BASE     = APBPERIPH_BASE + $0000B000;
+  SYSCFG_BASE   = APBPERIPH_BASE + $00010000;
+  VREFBUF_BASE  = APBPERIPH_BASE + $00010030;
+  COMP1_BASE    = SYSCFG_BASE + $0200;
+  COMP2_BASE    = SYSCFG_BASE + $0204;
+  ADC1_BASE     = APBPERIPH_BASE + $00012400;
+  ADC1_COMMON_BASE= APBPERIPH_BASE + $00012708;
+  ADC_BASE      = ADC1_COMMON_BASE;
+  TIM1_BASE     = APBPERIPH_BASE + $00012C00;
+  SPI1_BASE     = APBPERIPH_BASE + $00013000;
+  USART1_BASE   = APBPERIPH_BASE + $00013800;
+  TIM15_BASE    = APBPERIPH_BASE + $00014000;
+  TIM16_BASE    = APBPERIPH_BASE + $00014400;
+  TIM17_BASE    = APBPERIPH_BASE + $00014800;
+  DBG_BASE      = APBPERIPH_BASE + $00015800;
+  DMA1_BASE     = AHBPERIPH_BASE;
+  DMAMUX1_BASE  = AHBPERIPH_BASE + $00000800;
+  RCC_BASE      = AHBPERIPH_BASE + $00001000;
+  EXTI_BASE     = AHBPERIPH_BASE + $00001800;
+  FLASH_R_BASE  = AHBPERIPH_BASE + $00002000;
+  CRC_BASE      = AHBPERIPH_BASE + $00003000;
+  DMA1_Channel1_BASE= DMA1_BASE + $00000008;
+  DMA1_Channel2_BASE= DMA1_BASE + $0000001C;
+  DMA1_Channel3_BASE= DMA1_BASE + $00000030;
+  DMA1_Channel4_BASE= DMA1_BASE + $00000044;
+  DMA1_Channel5_BASE= DMA1_BASE + $00000058;
+  DMA1_Channel6_BASE= DMA1_BASE + $0000006C;
+  DMA1_Channel7_BASE= DMA1_BASE + $00000080;
+  DMAMUX1_Channel0_BASE= DMAMUX1_BASE;
+  DMAMUX1_Channel1_BASE= DMAMUX1_BASE + $00000004;
+  DMAMUX1_Channel2_BASE= DMAMUX1_BASE + $00000008;
+  DMAMUX1_Channel3_BASE= DMAMUX1_BASE + $0000000C;
+  DMAMUX1_Channel4_BASE= DMAMUX1_BASE + $00000010;
+  DMAMUX1_Channel5_BASE= DMAMUX1_BASE + $00000014;
+  DMAMUX1_Channel6_BASE= DMAMUX1_BASE + $00000018;
+  DMAMUX1_RequestGenerator0_BASE= DMAMUX1_BASE + $00000100;
+  DMAMUX1_RequestGenerator1_BASE= DMAMUX1_BASE + $00000104;
+  DMAMUX1_RequestGenerator2_BASE= DMAMUX1_BASE + $00000108;
+  DMAMUX1_RequestGenerator3_BASE= DMAMUX1_BASE + $0000010C;
+  DMAMUX1_ChannelStatus_BASE= DMAMUX1_BASE + $00000080;
+  DMAMUX1_RequestGenStatus_BASE= DMAMUX1_BASE + $00000140;
+  GPIOA_BASE    = IOPORT_BASE + $00000000;
+  GPIOB_BASE    = IOPORT_BASE + $00000400;
+  GPIOC_BASE    = IOPORT_BASE + $00000800;
+  GPIOD_BASE    = IOPORT_BASE + $00000C00;
+  GPIOF_BASE    = IOPORT_BASE + $00001400;
+  PACKAGE_BASE  = $1FFF7500;
+  UID_BASE      = $1FFF7590;
+  FLASHSIZE_BASE= $1FFF75E0;
+
+var
+  TIM2          : TTIM_Registers absolute TIM2_BASE;
+  TIM3          : TTIM_Registers absolute TIM3_BASE;
+  TIM6          : TTIM_Registers absolute TIM6_BASE;
+  TIM7          : TTIM_Registers absolute TIM7_BASE;
+  TIM14         : TTIM_Registers absolute TIM14_BASE;
+  RTC           : TRTC_Registers absolute RTC_BASE;
+  TAMP          : TTAMP_Registers absolute TAMP_BASE;
+  WWDG          : TWWDG_Registers absolute WWDG_BASE;
+  IWDG          : TIWDG_Registers absolute IWDG_BASE;
+  SPI2          : TSPI_Registers absolute SPI2_BASE;
+  USART2        : TUSART_Registers absolute USART2_BASE;
+  USART3        : TUSART_Registers absolute USART3_BASE;
+  USART4        : TUSART_Registers absolute USART4_BASE;
+  I2C1          : TI2C_Registers absolute I2C1_BASE;
+  I2C2          : TI2C_Registers absolute I2C2_BASE;
+  LPTIM1        : TLPTIM_Registers absolute LPTIM1_BASE;
+  PWR           : TPWR_Registers absolute PWR_BASE;
+  RCC           : TRCC_Registers absolute RCC_BASE;
+  EXTI          : TEXTI_Registers absolute EXTI_BASE;
+  DAC1          : TDAC_Registers absolute DAC1_BASE;
+  DAC           : TDAC_Registers absolute DAC_BASE;
+  LPUART1       : TUSART_Registers absolute LPUART1_BASE;
+  LPTIM2        : TLPTIM_Registers absolute LPTIM2_BASE;
+  CEC           : TCEC_Registers absolute CEC_BASE;
+  SYSCFG        : TSYSCFG_Registers absolute SYSCFG_BASE;
+  VREFBUF       : TVREFBUF_Registers absolute VREFBUF_BASE;
+  COMP1         : TCOMP_Registers absolute COMP1_BASE;
+  COMP2         : TCOMP_Registers absolute COMP2_BASE;
+  COMP12_COMMON : TCOMP_Common_Registers absolute COMP1_BASE;
+  TIM1          : TTIM_Registers absolute TIM1_BASE;
+  SPI1          : TSPI_Registers absolute SPI1_BASE;
+  USART1        : TUSART_Registers absolute USART1_BASE;
+  TIM15         : TTIM_Registers absolute TIM15_BASE;
+  TIM16         : TTIM_Registers absolute TIM16_BASE;
+  TIM17         : TTIM_Registers absolute TIM17_BASE;
+  DMA1          : TDMA_Registers absolute DMA1_BASE;
+  FLASH         : TFLASH_Registers absolute FLASH_R_BASE;
+  CRC           : TCRC_Registers absolute CRC_BASE;
+  GPIOA         : TGPIO_Registers absolute GPIOA_BASE;
+  GPIOB         : TGPIO_Registers absolute GPIOB_BASE;
+  GPIOC         : TGPIO_Registers absolute GPIOC_BASE;
+  GPIOD         : TGPIO_Registers absolute GPIOD_BASE;
+  GPIOF         : TGPIO_Registers absolute GPIOF_BASE;
+  ADC1          : TADC_Registers absolute ADC1_BASE;
+  ADC1_COMMON   : TADC_Common_Registers absolute ADC1_COMMON_BASE;
+  UCPD1         : TUCPD_Registers absolute UCPD1_BASE;
+  UCPD2         : TUCPD_Registers absolute UCPD2_BASE;
+  DMA1_Channel1 : TDMA_Channel_Registers absolute DMA1_Channel1_BASE;
+  DMA1_Channel2 : TDMA_Channel_Registers absolute DMA1_Channel2_BASE;
+  DMA1_Channel3 : TDMA_Channel_Registers absolute DMA1_Channel3_BASE;
+  DMA1_Channel4 : TDMA_Channel_Registers absolute DMA1_Channel4_BASE;
+  DMA1_Channel5 : TDMA_Channel_Registers absolute DMA1_Channel5_BASE;
+  DMA1_Channel6 : TDMA_Channel_Registers absolute DMA1_Channel6_BASE;
+  DMA1_Channel7 : TDMA_Channel_Registers absolute DMA1_Channel7_BASE;
+  DMAMUX1       : TDMAMUX_Channel_Registers absolute DMAMUX1_BASE;
+  DMAMUX1_Channel0: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel0_BASE;
+  DMAMUX1_Channel1: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel1_BASE;
+  DMAMUX1_Channel2: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel2_BASE;
+  DMAMUX1_Channel3: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel3_BASE;
+  DMAMUX1_Channel4: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel4_BASE;
+  DMAMUX1_Channel5: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel5_BASE;
+  DMAMUX1_Channel6: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel6_BASE;
+  DMAMUX1_RequestGenerator0: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator0_BASE;
+  DMAMUX1_RequestGenerator1: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator1_BASE;
+  DMAMUX1_RequestGenerator2: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator2_BASE;
+  DMAMUX1_RequestGenerator3: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator3_BASE;
+  DMAMUX1_ChannelStatus: TDMAMUX_ChannelStatus_Registers absolute DMAMUX1_ChannelStatus_BASE;
+  DMAMUX1_RequestGenStatus: TDMAMUX_RequestGenStatus_Registers absolute DMAMUX1_RequestGenStatus_BASE;
+  DBG           : TDBG_Registers absolute DBG_BASE;
+
+implementation
+
+procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
+procedure HardFault_interrupt; external name 'HardFault_interrupt';
+procedure SVC_interrupt; external name 'SVC_interrupt';
+procedure PendSV_interrupt; external name 'PendSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure WWDG_interrupt; external name 'WWDG_interrupt';
+procedure PVD_interrupt; external name 'PVD_interrupt';
+procedure RTC_TAMP_interrupt; external name 'RTC_TAMP_interrupt';
+procedure FLASH_interrupt; external name 'FLASH_interrupt';
+procedure RCC_interrupt; external name 'RCC_interrupt';
+procedure EXTI0_1_interrupt; external name 'EXTI0_1_interrupt';
+procedure EXTI2_3_interrupt; external name 'EXTI2_3_interrupt';
+procedure EXTI4_15_interrupt; external name 'EXTI4_15_interrupt';
+procedure UCPD1_2_interrupt; external name 'UCPD1_2_interrupt';
+procedure DMA1_Channel1_interrupt; external name 'DMA1_Channel1_interrupt';
+procedure DMA1_Channel2_3_interrupt; external name 'DMA1_Channel2_3_interrupt';
+procedure DMA1_Ch4_7_DMAMUX1_OVR_interrupt; external name 'DMA1_Ch4_7_DMAMUX1_OVR_interrupt';
+procedure ADC1_COMP_interrupt; external name 'ADC1_COMP_interrupt';
+procedure TIM1_BRK_UP_TRG_COM_interrupt; external name 'TIM1_BRK_UP_TRG_COM_interrupt';
+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
+procedure TIM2_interrupt; external name 'TIM2_interrupt';
+procedure TIM3_interrupt; external name 'TIM3_interrupt';
+procedure TIM6_DAC_LPTIM1_interrupt; external name 'TIM6_DAC_LPTIM1_interrupt';
+procedure TIM7_LPTIM2_interrupt; external name 'TIM7_LPTIM2_interrupt';
+procedure TIM14_interrupt; external name 'TIM14_interrupt';
+procedure TIM15_interrupt; external name 'TIM15_interrupt';
+procedure TIM16_interrupt; external name 'TIM16_interrupt';
+procedure TIM17_interrupt; external name 'TIM17_interrupt';
+procedure I2C1_interrupt; external name 'I2C1_interrupt';
+procedure I2C2_interrupt; external name 'I2C2_interrupt';
+procedure SPI1_interrupt; external name 'SPI1_interrupt';
+procedure SPI2_interrupt; external name 'SPI2_interrupt';
+procedure USART1_interrupt; external name 'USART1_interrupt';
+procedure USART2_interrupt; external name 'USART2_interrupt';
+procedure USART3_4_LPUART1_interrupt; external name 'USART3_4_LPUART1_interrupt';
+procedure CEC_interrupt; external name 'CEC_interrupt';
+
+
+{$i cortexm0_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+  .section ".init.interrupt_vectors"
+  interrupt_vectors:
+  .long _stack_top
+  .long Startup
+  .long NonMaskableInt_interrupt
+  .long HardFault_interrupt
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long 0
+  .long SVC_interrupt
+  .long 0
+  .long 0
+  .long PendSV_interrupt
+  .long SysTick_interrupt
+  .long WWDG_interrupt
+  .long PVD_interrupt
+  .long RTC_TAMP_interrupt
+  .long FLASH_interrupt
+  .long RCC_interrupt
+  .long EXTI0_1_interrupt
+  .long EXTI2_3_interrupt
+  .long EXTI4_15_interrupt
+  .long UCPD1_2_interrupt
+  .long DMA1_Channel1_interrupt
+  .long DMA1_Channel2_3_interrupt
+  .long DMA1_Ch4_7_DMAMUX1_OVR_interrupt
+  .long ADC1_COMP_interrupt
+  .long TIM1_BRK_UP_TRG_COM_interrupt
+  .long TIM1_CC_interrupt
+  .long TIM2_interrupt
+  .long TIM3_interrupt
+  .long TIM6_DAC_LPTIM1_interrupt
+  .long TIM7_LPTIM2_interrupt
+  .long TIM14_interrupt
+  .long TIM15_interrupt
+  .long TIM16_interrupt
+  .long TIM17_interrupt
+  .long I2C1_interrupt
+  .long I2C2_interrupt
+  .long SPI1_interrupt
+  .long SPI2_interrupt
+  .long USART1_interrupt
+  .long USART2_interrupt
+  .long USART3_4_LPUART1_interrupt
+  .long CEC_interrupt
+
+  .weak NonMaskableInt_interrupt
+  .weak HardFault_interrupt
+  .weak SVC_interrupt
+  .weak PendSV_interrupt
+  .weak SysTick_interrupt
+  .weak WWDG_interrupt
+  .weak PVD_interrupt
+  .weak RTC_TAMP_interrupt
+  .weak FLASH_interrupt
+  .weak RCC_interrupt
+  .weak EXTI0_1_interrupt
+  .weak EXTI2_3_interrupt
+  .weak EXTI4_15_interrupt
+  .weak UCPD1_2_interrupt
+  .weak DMA1_Channel1_interrupt
+  .weak DMA1_Channel2_3_interrupt
+  .weak DMA1_Ch4_7_DMAMUX1_OVR_interrupt
+  .weak ADC1_COMP_interrupt
+  .weak TIM1_BRK_UP_TRG_COM_interrupt
+  .weak TIM1_CC_interrupt
+  .weak TIM2_interrupt
+  .weak TIM3_interrupt
+  .weak TIM6_DAC_LPTIM1_interrupt
+  .weak TIM7_LPTIM2_interrupt
+  .weak TIM14_interrupt
+  .weak TIM15_interrupt
+  .weak TIM16_interrupt
+  .weak TIM17_interrupt
+  .weak I2C1_interrupt
+  .weak I2C2_interrupt
+  .weak SPI1_interrupt
+  .weak SPI2_interrupt
+  .weak USART1_interrupt
+  .weak USART2_interrupt
+  .weak USART3_4_LPUART1_interrupt
+  .weak CEC_interrupt
+
+  .set NonMaskableInt_interrupt, Haltproc
+  .set HardFault_interrupt, Haltproc
+  .set SVC_interrupt, Haltproc
+  .set PendSV_interrupt, Haltproc
+  .set SysTick_interrupt, Haltproc
+  .set WWDG_interrupt, Haltproc
+  .set PVD_interrupt, Haltproc
+  .set RTC_TAMP_interrupt, Haltproc
+  .set FLASH_interrupt, Haltproc
+  .set RCC_interrupt, Haltproc
+  .set EXTI0_1_interrupt, Haltproc
+  .set EXTI2_3_interrupt, Haltproc
+  .set EXTI4_15_interrupt, Haltproc
+  .set UCPD1_2_interrupt, Haltproc
+  .set DMA1_Channel1_interrupt, Haltproc
+  .set DMA1_Channel2_3_interrupt, Haltproc
+  .set DMA1_Ch4_7_DMAMUX1_OVR_interrupt, Haltproc
+  .set ADC1_COMP_interrupt, Haltproc
+  .set TIM1_BRK_UP_TRG_COM_interrupt, Haltproc
+  .set TIM1_CC_interrupt, Haltproc
+  .set TIM2_interrupt, Haltproc
+  .set TIM3_interrupt, Haltproc
+  .set TIM6_DAC_LPTIM1_interrupt, Haltproc
+  .set TIM7_LPTIM2_interrupt, Haltproc
+  .set TIM14_interrupt, Haltproc
+  .set TIM15_interrupt, Haltproc
+  .set TIM16_interrupt, Haltproc
+  .set TIM17_interrupt, Haltproc
+  .set I2C1_interrupt, Haltproc
+  .set I2C2_interrupt, Haltproc
+  .set SPI1_interrupt, Haltproc
+  .set SPI2_interrupt, Haltproc
+  .set USART1_interrupt, Haltproc
+  .set USART2_interrupt, Haltproc
+  .set USART3_4_LPUART1_interrupt, Haltproc
+  .set CEC_interrupt, Haltproc
+
+  .text
+  end;
+end.
diff --git a/utils/fpcm/fpcmake.inc b/utils/fpcm/fpcmake.inc
index 7a449ea737..e1e3022c2f 100644
--- a/utils/fpcm/fpcmake.inc
+++ b/utils/fpcm/fpcmake.inc
@@ -1,7 +1,7 @@
 {$ifdef Delphi}
-const fpcmakeini : array[0..247] of string[240]=(
+const fpcmakeini : array[0..249] of string[240]=(
 {$else Delphi}
-const fpcmakeini : array[0..247,1..240] of char=(
+const fpcmakeini : array[0..249,1..240] of char=(
 {$endif Delphi}
   ';'#010+
   '; Templates used by fpcmake to create a Makefile from Makefile.fpc'#010+
@@ -317,13 +317,29 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'override FPCOPT+=-Cp$(SUBARCH)'#010+
   'endif'#010+
   #010+
+  'ifeq ($(FULL_TARGET),xtensa-freertos)'#010+
+  'ifeq ($(SUBARCH),)'#010+
+  '$(error When compiling for xtensa-freertos, a sub-architecture (e.g. S'+
+  'UBARCH=lx106 or SUBARCH=lx6) must be defined)'#010+
+  'endif'#010+
+  'overr','ide FPCOPT+=-Cp$(SUBARCH)'#010+
+  'endif'#010+
+  #010+
+  'ifeq ($(FULL_TARGET),arm-freertos)'#010+
+  'ifeq ($(SUBARCH),)'#010+
+  '$(error When compiling for arm-freertos, a sub-architecture (e.g. SUBA'+
+  'RCH=armv6m or SUBARCH=armv7em) must be defined)'#010+
+  'endif'#010+
+  'override FPCOPT+=-Cp$(SUBARCH',')'#010+
+  'endif'#010+
+  #010+
   '# Full name of the target, including CPU and OS. For OSs limited'#010+
   '# to 8.3 we only use the target OS'#010+
   'ifneq ($(findstring $(OS_SOURCE),$(LIMIT83fs)),)'#010+
   'TARGETSUFFIX=$(OS_TARGET)'#010+
-  'SOURCESUF','FIX=$(OS_SOURCE)'#010+
+  'SOURCESUFFIX=$(OS_SOURCE)'#010+
   'else'#010+
-  'ifneq ($(findstring $(OS_TARGET),$(LIMIT83fs)),)'#010+
+  'ifneq ($(findstring $(OS_','TARGET),$(LIMIT83fs)),)'#010+
   'TARGETSUFFIX=$(OS_TARGET)'#010+
   'else'#010+
   'TARGETSUFFIX=$(FULL_TARGET)'#010+
@@ -333,15 +349,15 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Cross compile flag'#010+
   'ifneq ($(FULL_TARGET),$(FULL_SOURCE))'#010+
-  'CROSSCOMPI','LE=1'#010+
+  'CROSSCOMPILE=1'#010+
   'endif'#010+
   #010+
-  '# Check if the Makefile supports this target, but not'#010+
+  '# Check if the Makefile supports th','is target, but not'#010+
   '# when the make target is to rebuild the makefile'#010+
   'ifeq ($(findstring makefile,$(MAKECMDGOALS)),)'#010+
   'ifeq ($(findstring $(FULL_TARGET),$(MAKEFILETARGETS)),)'#010+
-  '$(error The Makefile ','doesn'#039't support target $(FULL_TARGET), plea'+
-  'se run fpcmake first)'#010+
+  '$(error The Makefile doesn'#039't support target $(FULL_TARGET), please'+
+  ' r','un fpcmake first)'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -352,8 +368,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'BSDhier=1'#010+
   'endif'#010+
   #010+
-  '# Detect Linux, will also use',' its own directory hierarchy.'#010+
-  'ifeq ($(OS_TARGET),linux)'#010+
+  '# Detect Linux, will also use its own directory hierarchy.'#010+
+  'ifeq ($(OS_TARGET','),linux)'#010+
   'linuxHier=1'#010+
   'endif'#010+
   #010+
@@ -367,53 +383,52 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'export BUILDNATIVE'#010+
   'endif'#010+
   #010+
-  'export OS_TARGET OS_SOURCE ARCH CPU','_TARGET CPU_SOURCE FULL_TARGET FU'+
-  'LL_SOURCE TARGETSUFFIX SOURCESUFFIX CROSSCOMPILE'#010+
+  'export OS_TARGET OS_SOURCE ARCH CPU_TARGET CPU_SOURCE FULL_TARGET FULL'+
+  '_SOURCE TARG','ETSUFFIX SOURCESUFFIX CROSSCOMPILE'#010+
   #010+
   '[fpmakefpcdetect]'#010+
   '#####################################################################'#010+
   '# FPC Binary and Version Detection'#010+
-  '##################################','##################################'+
-  '#'#010+
-  '# If FPCFPMAKE is not set and we'#039're cross-compiling, try to find a'+
-  #010+
+  '#####################################################################'#010+
+  '# If FPCFPM','AKE is not set and we'#039're cross-compiling, try to find'+
+  ' a'#010+
   '# native compiler.'#010+
   'ifndef FPCFPMAKE'#010+
   #010+
   'ifdef CROSSCOMPILE'#010+
   '# Search for the (native) ppc compiler which is used to do the latest '+
   'build'#010+
-  '# of ','the native rtl'#010+
+  '# of the native rtl'#010+
   #010+
-  'ifeq ($(strip $(wildcard $(addsuffix /compiler/ppc$(SRCEXEEXT),$(FPCDI'+
-  'R)))),)'#010+
+  'ifeq ($(strip $(wildcard $(adds','uffix /compiler/ppc$(SRCEXEEXT),$(FPC'+
+  'DIR)))),)'#010+
   '# If that compiler is not found, use the common, installed native comp'+
   'iler'#010+
   '# Note that in this case FPCFPMAKE is not exported, because it could b'+
-  'e',' that'#010+
-  '# a more suitable compiler is compiled later on'#010+
+  'e that'#010+
+  '# a more suitable compiler is compiled la','ter on'#010+
   '# check if fpc exists'#010+
   'FPCPROG:=$(strip $(wildcard $(addsuffix /fpc$(SRCEXEEXT),$(SEARCHPATH)'+
   ')))'#010+
   'ifneq ($(FPCPROG),)'#010+
   'FPCPROG:=$(firstword $(FPCPROG))'#010+
   'FPCFPMAKE:=$(shell $(FPCPROG) -PB)'#010+
-  '# ','if a native compiler is not found, fall back to fpc'#010+
+  '# if a native compiler is not found, fall back to',' fpc'#010+
   'ifeq ($(strip $(wildcard $(FPCFPMAKE))),)'#010+
   'FPCFPMAKE:=$(firstword $(FPCPROG))'#010+
   'endif'#010+
   'else'#010+
   '# fpc binary not found, fallback to ppc386'#010+
-  'override FPCFPMAKE=$(firstword $(strip $(wildcard $(addsu','ffix /ppc38'+
-  '6$(SRCEXEEXT),$(SEARCHPATH)))))'#010+
-  'endif'#010+
+  'override FPCFPMAKE=$(firstword $(strip $(wildcard $(addsuffix /ppc386$'+
+  '(SRCEXEEXT),$(SEARCHPATH)))))'#010+
+  'endi','f'#010+
   'else'#010+
   '# Use the ppc compiler. Because the path to the compiler is relative, '+
   'do not'#010+
   '# evaluate the variable here, but do that on the fly.'#010+
-  'FPCFPMAKE=$(strip $(wildcard $(addsuffix /compiler/ppc$','(SRCEXEEXT),$'+
-  '(FPCDIR))))'#010+
-  'FPMAKE_SKIP_CONFIG=-n'#010+
+  'FPCFPMAKE=$(strip $(wildcard $(addsuffix /compiler/ppc$(SRCEXEEXT),$(F'+
+  'PCDIR))))'#010+
+  'FPMAKE_SKIP_CONFIG=-n'#010,
   'export FPCFPMAKE'#010+
   'export FPMAKE_SKIP_CONFIG'#010+
   'endif'#010+
@@ -427,19 +442,19 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   #010+
   '[fpcdircheckenv]'#010+
-  '###################################################################','#'+
-  '#'#010+
-  '# FPCDIR Setting'#010+
   '#####################################################################'#010+
+  '# FPCDIR Setting'#010+
+  '###########################','#########################################'+
+  '#'#010+
   #010+
   '# Test FPCDIR to look if the RTL dir exists'#010+
   'ifdef FPCDIR'#010+
   'override FPCDIR:=$(subst \,/,$(FPCDIR))'#010+
   'ifeq ($(wildcard $(addprefix $(FPCDIR)/,rtl)),)'#010+
-  'over','ride FPCDIR=wrong'#010+
+  'override FPCDIR=wrong'#010+
   'endif'#010+
   'else'#010+
-  'override FPCDIR=wrong'#010+
+  'override FPCDIR=wr','ong'#010+
   'endif'#010+
   #010+
   '# Default FPCDIR from Makefile.fpc'#010+
@@ -447,12 +462,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifeq ($(FPCDIR),wrong)'#010+
   'override FPCDIR:=$(subst \,/,$(DEFAULT_FPCDIR))'#010+
   'ifeq ($(wildcard $(addprefix $(FPCDIR)/,rtl)),)'#010+
-  'overrid','e FPCDIR=wrong'#010+
+  'override FPCDIR=wrong'#010+
   'endif'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  '[fpcdirdetect]'#010+
+  '[fpcdirdetect',']'#010+
   '# Detect FPCDIR'#010+
   'ifeq ($(FPCDIR),wrong)'#010+
   'ifdef inUnix'#010+
@@ -460,14 +475,14 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifeq ($(wildcard $(FPCDIR)/units),)'#010+
   'override FPCDIR=/usr/lib/fpc/$(FPC_VERSION)'#010+
   'endif'#010+
-  'els','e'#010+
-  'override FPCDIR:=$(subst /$(FPC),,$(firstword $(strip $(wildcard $(add'+
-  'suffix /$(FPC),$(SEARCHPATH))))))'#010+
+  'else'#010+
+  'override FPCDIR:=$(subst /$(FPC),,$(firstword',' $(strip $(wildcard $(a'+
+  'ddsuffix /$(FPC),$(SEARCHPATH))))))'#010+
   'override FPCDIR:=$(FPCDIR)/..'#010+
   'ifeq ($(wildcard $(addprefix $(FPCDIR)/,rtl)),)'#010+
   'override FPCDIR:=$(FPCDIR)/..'#010+
-  'ifeq ($(wildcard $(addpref','ix $(FPCDIR)/,rtl)),)'#010+
-  'override FPCDIR:=$(BASEDIR)'#010+
+  'ifeq ($(wildcard $(addprefix $(FPCDIR)/,rtl)),)'#010+
+  'override FPCDIR:=$(BASEDI','R)'#010+
   'ifeq ($(wildcard $(addprefix $(FPCDIR)/,rtl)),)'#010+
   'override FPCDIR=c:/pp'#010+
   'endif'#010+
@@ -478,10 +493,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Cross binaries dir'#010+
   'ifndef CROSSBINDIR'#010+
-  'CROSSBINDIR:=$(wildcard $(FPCDIR)/bin/$(TARGETSUF','FIX))'#010+
+  'CROSSBINDIR:=$(wildcard $(FPCDIR)/bin/$(TARGETSUFFIX))'#010+
   'endif'#010+
   #010+
-  '# Default binutils prefix for cross compile when the'#010+
+  '# Default binutils prefix for cros','s compile when the'#010+
   '# crossbindir is not set (except for Darwin)'#010+
   'ifneq ($(findstring $(OS_TARGET),darwin iphonesim),)'#010+
   'ifeq ($(OS_SOURCE),darwin)'#010+
@@ -489,18 +504,18 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   'endif'#010+
   #010+
-  'ifndef BINUTILSPREFI','X'#010+
+  'ifndef BINUTILSPREFIX'#010+
   'ifndef CROSSBINDIR'#010+
   'ifdef CROSSCOMPILE'#010+
-  'ifneq ($(OS_TARGET),msdos)'#010+
+  'ifneq (','$(OS_TARGET),msdos)'#010+
   'ifndef DARWIN2DARWIN'#010+
   'ifneq ($(CPU_TARGET),jvm)'#010+
   'BINUTILSPREFIX=$(CPU_TARGET)-$(OS_TARGET)-'#010+
   #010+
   '# For Android use standard NDK prefixes'#010+
   'ifeq ($(OS_TARGET),android)'#010+
-  'ifeq ($(CPU_TA','RGET),arm)'#010+
-  'BINUTILSPREFIX=arm-linux-androideabi-'#010+
+  'ifeq ($(CPU_TARGET),arm)'#010+
+  'BINUTILSPREFIX=arm-linux-androideabi','-'#010+
   'else'#010+
   'ifeq ($(CPU_TARGET),i386)'#010+
   'BINUTILSPREFIX=i686-linux-android-'#010+
@@ -515,19 +530,19 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'else'#010+
   'BINUTILSPREFIX=$(OS_TARGET)-'#010+
   'endif'#010+
-  'endif',#010+
+  'endif'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  '# Try first the full target name, otherwise try only'#010+
+  '# Try first the full target name,',' otherwise try only'#010+
   '# the OS for backwards compatibility'#010+
   'UNITSDIR:=$(wildcard $(FPCDIR)/units/$(TARGETSUFFIX))'#010+
   'ifeq ($(UNITSDIR),)'#010+
   'UNITSDIR:=$(wildcard $(FPCDIR)/units/$(OS_TARGET))'#010+
   'endif'#010+
   #010+
-  '# Pa','ckages dir'#010+
-  'PACKAGESDIR:=$(wildcard $(FPCDIR) $(FPCDIR)/packages)'#010+
+  '# Packages dir'#010+
+  'PACKAGESDIR:=$(wildcard $(FPCDIR) $(','FPCDIR)/packages)'#010+
   #010+
   #010+
   '[shelltools]'#010+
@@ -535,7 +550,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Shell tools'#010+
   '#####################################################################'#010+
   #010+
-  '# Ech','o that can redir (must be able run in the default OS shell)'#010+
+  '# Echo that can redir (must be able run in the defau','lt OS shell)'#010+
   'ifndef ECHOREDIR'#010+
   'ifndef inUnix'#010+
   'ECHOREDIR=echo'#010+
@@ -551,10 +566,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Copy a whole tree'#010+
   'ifndef COPYTREE'#010+
-  'COPYT','REE:=$(CPPROG) -Rfp'#010+
+  'COPYTREE:=$(CPPROG) -Rfp'#010+
   'endif'#010+
   #010+
-  '# Copy a whole tree'#010+
+  '# Copy a whole tree'#010,
   'ifndef MKDIRTREE'#010+
   'MKDIRTREE:=$(MKDIRPROG) -p'#010+
   'endif'#010+
@@ -570,11 +585,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# Check deltree program'#010+
-  'ifn','def DELTREE'#010+
+  'ifndef DELTREE'#010+
   'DELTREE:=$(RMPROG) -rf'#010+
   'endif'#010+
   #010+
-  '# To install files'#010+
+  '# To ','install files'#010+
   'ifndef INSTALL'#010+
   'ifdef inUnix'#010+
   'INSTALL:=$(GINSTALL) -c -m 644'#010+
@@ -586,13 +601,13 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# To install programs'#010+
   'ifndef INSTALLEXE'#010+
   'ifdef inUnix'#010+
-  'INSTALLEXE:=$(GINSTALL) -c -m 75','5'#010+
+  'INSTALLEXE:=$(GINSTALL) -c -m 755'#010+
   'else'#010+
   'INSTALLEXE:=$(COPY)'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  '# To make a directory.'#010+
+  '# To ma','ke a directory.'#010+
   'ifndef MKDIR'#010+
   'MKDIR:=$(GINSTALL) -m 755 -d'#010+
   'endif'#010+
@@ -602,9 +617,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   #010+
   '[defaultdirs]'#010+
-  '#######################################','#############################'+
-  '#'#010+
-  '# Default Directories'#010+
+  '#####################################################################'#010+
+  '# Default Direct','ories'#010+
   '#####################################################################'#010+
   #010+
   '# Units dir'#010+
@@ -613,8 +627,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# Units dir'#010+
-  'ifdef REQUIRE_PACKAGESD','IR'#010+
-  'override PACKAGESDIR+=$(REQUIRE_PACKAGESDIR)'#010+
+  'ifdef REQUIRE_PACKAGESDIR'#010+
+  'override PACKAGESDIR+=$(REQUIRE_PACKAGESDIR)',#010+
   'endif'#010+
   #010+
   #010+
@@ -623,8 +637,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# use the source os as default'#010+
   'ifdef ZIPINSTALL'#010+
   '# Zipinstall'#010+
-  'ifneq ($(','findstring $(OS_TARGET),$(UNIXs)),)'#010+
-  'UNIXHier=1'#010+
+  'ifneq ($(findstring $(OS_TARGET),$(UNIXs)),)'#010+
+  'UNIXHier=1'#010,
   'endif'#010+
   'else'#010+
   '# Normal install'#010+
@@ -636,11 +650,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# When install prefix is not set try to use prefix'#010+
   'ifndef INSTALL_PREFIX'#010+
   'ifdef PREFIX'#010+
-  'INSTALL_PR','EFIX=$(PREFIX)'#010+
+  'INSTALL_PREFIX=$(PREFIX)'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  '# set the prefix directory where to install everything'#010+
+  '# set the prefix di','rectory where to install everything'#010+
   'ifndef INSTALL_PREFIX'#010+
   'ifdef UNIXHier'#010+
   'INSTALL_PREFIX=/usr/local'#010+
@@ -649,32 +663,32 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'INSTALL_BASEDIR:=/pp'#010+
   'else'#010+
   'INSTALL_BASEDIR:=/$(PACKAGE_NAME)'#010+
-  'endi','f'#010+
+  'endif'#010+
   'endif'#010+
   'endif'#010+
   'export INSTALL_PREFIX'#010+
   #010+
-  '# Export also INSTALL_SOURCESUBDIR set so it will be'#010+
+  '# Export a','lso INSTALL_SOURCESUBDIR set so it will be'#010+
   '# used recursively for all subdirs'#010+
   'ifdef INSTALL_FPCSUBDIR'#010+
   'export INSTALL_FPCSUBDIR'#010+
   'endif'#010+
   #010+
   '# Where to place the resulting zip files'#010+
-  'ifndef DIST_DESTDI','R'#010+
+  'ifndef DIST_DESTDIR'#010+
   'DIST_DESTDIR:=$(BASEDIR)'#010+
   'endif'#010+
-  'export DIST_DESTDIR'#010+
+  'export DIST_DE','STDIR'#010+
   #010+
   '# EXE/PPU Target directories'#010+
   'ifndef COMPILER_UNITTARGETDIR'#010+
   'ifdef PACKAGEDIR_MAIN'#010+
   'COMPILER_UNITTARGETDIR=$(PACKAGEDIR_MAIN)/units/$(TARGETSUFFIX)'#010+
   'else'#010+
-  'COMPILER_UNITTARGETDIR=units/$(TARGE','TSUFFIX)'#010+
+  'COMPILER_UNITTARGETDIR=units/$(TARGETSUFFIX)'#010+
   'endif'#010+
   'endif'#010+
-  'ifndef COMPILER_TARGETDIR'#010+
+  'ifndef COMPILER_TARGETDIR'#010,
   'COMPILER_TARGETDIR=.'#010+
   'endif'#010+
   #010+
@@ -683,7 +697,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Install Directories'#010+
   '#####################################################################'#010+
   #010+
-  '#',' set the base directory where to install everything'#010+
+  '# set the base directory where to install everyt','hing'#010+
   'ifndef INSTALL_BASEDIR'#010+
   'ifdef UNIXHier'#010+
   'ifdef INSTALL_FPCPACKAGE'#010+
@@ -691,10 +705,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'else'#010+
   'INSTALL_BASEDIR:=$(INSTALL_PREFIX)/lib/$(PACKAGE_NAME)'#010+
   'endif'#010+
-  'e','lse'#010+
+  'else'#010+
   'INSTALL_BASEDIR:=$(INSTALL_PREFIX)'#010+
   'endif'#010+
-  'endif'#010+
+  'en','dif'#010+
   #010+
   '# set the directory where to install the binaries'#010+
   'ifndef INSTALL_BINDIR'#010+
@@ -702,7 +716,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'INSTALL_BINDIR:=$(INSTALL_PREFIX)/bin'#010+
   'else'#010+
   'INSTALL_BINDIR:=$(INSTALL_BASEDIR)/bin'#010+
-  '# for FPC packages ','install the binaries under their target subdir'#010+
+  '# for FPC packages install the binaries under their target subdir'#010,
   'ifdef INSTALL_FPCPACKAGE'#010+
   'ifdef CROSSCOMPILE'#010+
   'ifdef CROSSINSTALL'#010+
@@ -711,9 +725,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'INSTALL_BINDIR:=$(INSTALL_BINDIR)/$(TARGETSUFFIX)'#010+
   'endif'#010+
   'else'#010+
-  'INSTALL_BINDIR',':=$(INSTALL_BINDIR)/$(TARGETSUFFIX)'#010+
-  'endif'#010+
+  'INSTALL_BINDIR:=$(INSTALL_BINDIR)/$(TARGETSUFFIX)'#010+
   'endif'#010+
+  'endif',#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -722,8 +736,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'INSTALL_UNITDIR:=$(INSTALL_BASEDIR)/units/$(TARGETSUFFIX)'#010+
   'ifdef INSTALL_FPCPACKAGE'#010+
   'ifdef PACKAGE_NAME'#010+
-  'INSTAL','L_UNITDIR:=$(INSTALL_UNITDIR)/$(PACKAGE_NAME)'#010+
-  'endif'#010+
+  'INSTALL_UNITDIR:=$(INSTALL_UNITDIR)/$(PACKAGE_NAME)'#010+
+  'e','ndif'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -736,8 +750,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   'endif'#010+
   #010+
-  '# Where the',' source files will be stored'#010+
-  'ifndef INSTALL_SOURCEDIR'#010+
+  '# Where the source files will be stored'#010+
+  'ifndef INSTALL_SOU','RCEDIR'#010+
   'ifdef UNIXHier'#010+
   'ifdef BSDhier'#010+
   'SRCPREFIXDIR=share/src'#010+
@@ -750,15 +764,15 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   'ifdef INSTALL_FPCPACKAGE'#010+
   'ifdef INSTALL_FPCSUBDIR'#010+
-  'INSTALL','_SOURCEDIR:=$(INSTALL_PREFIX)/$(SRCPREFIXDIR)/fpc-$(FPC_VERSI'+
+  'INSTALL_SOURCEDIR:=$(INSTALL_PREFIX)/$(SRCPREFIXDIR)/f','pc-$(FPC_VERSI'+
   'ON)/$(INSTALL_FPCSUBDIR)/$(PACKAGE_NAME)'#010+
   'else'#010+
   'INSTALL_SOURCEDIR:=$(INSTALL_PREFIX)/$(SRCPREFIXDIR)/fpc-$(FPC_VERSION'+
   ')/$(PACKAGE_NAME)'#010+
   'endif'#010+
   'else'#010+
-  'INSTALL_SOURCEDIR:=$(INSTALL_PREFI','X)/$(SRCPREFIXDIR)/$(PACKAGE_NAME)'+
-  '-$(PACKAGE_VERSION)'#010+
+  'INSTALL_SOURCEDIR:=$(INSTALL_PREFIX)/$(SRCPREFIXDIR)/$(PACKAGE_NAME)-$'+
+  '(PACKAGE_VE','RSION)'#010+
   'endif'#010+
   'else'#010+
   'ifdef INSTALL_FPCPACKAGE'#010+
@@ -766,10 +780,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'INSTALL_SOURCEDIR:=$(INSTALL_BASEDIR)/source/$(INSTALL_FPCSUBDIR)/$(PA'+
   'CKAGE_NAME)'#010+
   'else'#010+
-  'INSTALL_SOURCEDIR:=$(INSTALL_BASEDIR)/s','ource/$(PACKAGE_NAME)'#010+
+  'INSTALL_SOURCEDIR:=$(INSTALL_BASEDIR)/source/$(PACKAGE_NAME)'#010+
   'endif'#010+
   'else'#010+
-  'INSTALL_SOURCEDIR:=$(INSTALL_BASEDIR)/source'#010+
+  'INSTALL_SOURCE','DIR:=$(INSTALL_BASEDIR)/source'#010+
   'endif'#010+
   'endif'#010+
   'endif'#010+
@@ -781,21 +795,21 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'DOCPREFIXDIR=share/doc'#010+
   'else'#010+
   'ifdef linuxHier'#010+
-  'DOCPREFIXDI','R=share/doc'#010+
+  'DOCPREFIXDIR=share/doc'#010+
   'else'#010+
   'DOCPREFIXDIR=doc'#010+
   'endif'#010+
   'endif'#010+
-  'ifdef INSTALL_FPCPACKAGE'#010+
+  'i','fdef INSTALL_FPCPACKAGE'#010+
   'INSTALL_DOCDIR:=$(INSTALL_PREFIX)/$(DOCPREFIXDIR)/fpc-$(FPC_VERSION)/$'+
   '(PACKAGE_NAME)'#010+
   'else'#010+
   'INSTALL_DOCDIR:=$(INSTALL_PREFIX)/$(DOCPREFIXDIR)/$(PACKAGE_NAME)-$(PA'+
-  'CKAGE_VER','SION)'#010+
+  'CKAGE_VERSION)'#010+
   'endif'#010+
   'else'#010+
   'ifdef INSTALL_FPCPACKAGE'#010+
-  'INSTALL_DOCDIR:=$(INSTALL_BASEDIR)/doc/$(PACKAGE_NAME)'#010+
+  'INSTA','LL_DOCDIR:=$(INSTALL_BASEDIR)/doc/$(PACKAGE_NAME)'#010+
   'else'#010+
   'INSTALL_DOCDIR:=$(INSTALL_BASEDIR)/doc'#010+
   'endif'#010+
@@ -803,8 +817,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# Where to install the examples, under linux we use the doc dir'#010+
-  '# because the co','pytree command will create a subdir itself'#010+
-  'ifndef INSTALL_EXAMPLEDIR'#010+
+  '# because the copytree command will create a subdir itself'#010+
+  'ifnd','ef INSTALL_EXAMPLEDIR'#010+
   'ifdef UNIXHier'#010+
   'ifdef INSTALL_FPCPACKAGE'#010+
   #010+
@@ -813,10 +827,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   ')/$(PACKAGE_NAME)'#010+
   'else'#010+
   'ifdef linuxHier'#010+
-  'INSTALL','_EXAMPLEDIR:=$(INSTALL_DOCDIR)/examples'#010+
+  'INSTALL_EXAMPLEDIR:=$(INSTALL_DOCDIR)/examples'#010+
   'else'#010+
-  'INSTALL_EXAMPLEDIR:=$(INSTALL_PREFIX)/doc/fpc-$(FPC_VERSION)/examples/'+
-  '$(PACKAGE_NAME)'#010+
+  'IN','STALL_EXAMPLEDIR:=$(INSTALL_PREFIX)/doc/fpc-$(FPC_VERSION)/example'+
+  's/$(PACKAGE_NAME)'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -824,11 +838,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   'ifdef BSDhier'#010+
   'INSTALL_EXAMPLEDIR:=$(INSTALL_PREFIX)/share/examples/$(PACKAGE_NAME)-$'+
-  '(PACKA','GE_VERSION)'#010+
+  '(PACKAGE_VERSION)'#010+
   'else'#010+
   'ifdef linuxHier'#010+
-  'INSTALL_EXAMPLEDIR:=$(INSTALL_DOCDIR)/examples/$(PACKAGE_NAME)-$(PACKA'+
-  'GE_VERSION)'#010+
+  'INSTALL_EXAMPL','EDIR:=$(INSTALL_DOCDIR)/examples/$(PACKAGE_NAME)-$(PAC'+
+  'KAGE_VERSION)'#010+
   'else'#010+
   'INSTALL_EXAMPLEDIR:=$(INSTALL_PREFIX)/doc/$(PACKAGE_NAME)-$(PACKAGE_VE'+
   'RSION)'#010+
@@ -837,8 +851,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   'endif'#010+
   'else'#010+
-  'ifdef INSTALL_FPCPA','CKAGE'#010+
-  'INSTALL_EXAMPLEDIR:=$(INSTALL_BASEDIR)/examples/$(PACKAGE_NAME)'#010+
+  'ifdef INSTALL_FPCPACKAGE'#010+
+  'INSTALL_EXAMPLEDIR:=$(INSTALL_BASEDIR)/ex','amples/$(PACKAGE_NAME)'#010+
   'else'#010+
   'INSTALL_EXAMPLEDIR:=$(INSTALL_BASEDIR)/examples'#010+
   'endif'#010+
@@ -847,24 +861,23 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Where the some extra (data)files will be stored'#010+
   'ifndef INSTALL_DATADIR'#010+
-  'INSTALL_DATADIR=$(INSTALL','_BASEDIR)'#010+
+  'INSTALL_DATADIR=$(INSTALL_BASEDIR)'#010+
   'endif'#010+
   #010+
   'ifndef INSTALL_SHAREDDIR'#010+
-  'INSTALL_SHAREDDIR=$(INSTALL_PREFIX)/lib'#010+
+  'INSTA','LL_SHAREDDIR=$(INSTALL_PREFIX)/lib'#010+
   'endif'#010+
   #010+
   '#####################################################################'#010+
   '# Cross compile dirs'#010+
-  '############################################################','########'+
-  '#'#010+
+  '#####################################################################'#010+
   #010+
   'ifdef CROSSCOMPILE'#010+
-  '# Directory where the cross compile tools are stored.'#010+
+  '# Directory where',' the cross compile tools are stored.'#010+
   '# First check if they are available in FPCDIR. If no targets/ subdir'#010+
   '# is found use the targets/ subdir in INSTALL_BASEDIR.'#010+
   'ifndef CROSSBINDIR'#010+
-  'CROSSBINDIR:=','$(wildcard $(CROSSTARGETDIR)/bin/$(SOURCESUFFIX))'#010+
+  'CROSSBINDIR:=$(wildcard $(CROSSTARGETDIR)/bin/$(SOURCESUFFIX','))'#010+
   'ifeq ($(CROSSBINDIR),)'#010+
   'CROSSBINDIR:=$(wildcard $(INSTALL_BASEDIR)/cross/$(TARGETSUFFIX)/bin/$'+
   '(FULL_SOURCE))'#010+
@@ -876,20 +889,20 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   #010+
   '[dirlibc]'#010+
-  '# On linux, try to find where libg','cc.a is.'#010+
+  '# On linux, try to find where libgcc.a is.'#010+
   'ifeq ($(OS_SOURCE),linux)'#010+
   #010+
-  '# Amd64 to i386?'#010+
+  '# Amd64 to ','i386?'#010+
   'ifndef GCCLIBDIR'#010+
   'ifeq ($(CPU_TARGET),i386)'#010+
   'ifneq ($(findstring x86_64,$(shell uname -a)),)'#010+
   'ifeq ($(BINUTILSPREFIX),)'#010+
   'GCCLIBDIR:=$(shell dirname `gcc -m32 -print-libgcc-file-name`)'#010+
   'endif'#010+
-  'e','ndif'#010+
+  'endif'#010+
   'endif'#010+
   'ifeq ($(CPU_TARGET),powerpc64)'#010+
-  'ifeq ($(BINUTILSPREFIX),)'#010+
+  'ifeq ','($(BINUTILSPREFIX),)'#010+
   'GCCLIBDIR:=$(shell dirname `gcc -m64 -print-libgcc-file-name`)'#010+
   'endif'#010+
   'endif'#010+
@@ -897,21 +910,21 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Try cross gcc'#010+
   'ifndef GCCLIBDIR'#010+
-  'CROSSGCC=$(strip $(wildcard $(addsuffix /$(BINUTILSPREFIX',')gcc$(SRCEX'+
-  'EEXT),$(SEARCHPATH))))'#010+
-  'ifneq ($(CROSSGCC),)'#010+
+  'CROSSGCC=$(strip $(wildcard $(addsuffix /$(BINUTILSPREFIX)gcc$(SRCEXEE'+
+  'XT),$(SEARCHPATH))))'#010+
+  'ifneq ($(CROS','SGCC),)'#010+
   'GCCLIBDIR:=$(shell dirname `$(CROSSGCC) -print-libgcc-file-name`)'#010+
   'endif'#010+
   'endif'#010+
   #010+
   '# Other libraries from ld.so.conf'#010+
   'ifndef OTHERLIBDIR'#010+
-  'OTHERLIBDIR:=$(shell grep -v "^\#" /etc/ld.so.conf | ','awk '#039'{ ORS='+
-  '" "; print $1 }'#039')'#010+
+  'OTHERLIBDIR:=$(shell grep -v "^\#" /etc/ld.so.conf | awk '#039'{ ORS=" '+
+  '"; print $1 }'#039')'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  'ifdef inUnix'#010+
+  'ifdef',' inUnix'#010+
   'ifeq ($(OS_SOURCE),netbsd)'#010+
   'OTHERLIBDIR+=/usr/pkg/lib'#010+
   'endif'#010+
@@ -921,8 +934,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '[extensions]'#010+
   '#####################################################################'#010+
-  '# Default',' extensions'#010+
-  '#####################################################################'#010+
+  '# Default extensions'#010+
+  '###################################','#################################'+
+  '#'#010+
   #010+
   '# Default needed extensions (Go32v2,Linux)'#010+
   'BATCHEXT=.bat'#010+
@@ -934,9 +948,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'LTOEXT=.bc'#010+
   'ASMEXT=.s'#010+
   'SMARTEXT=.sl'#010+
-  'STATICLI','BEXT=.a'#010+
+  'STATICLIBEXT=.a'#010+
   'SHAREDLIBEXT=.so'#010+
-  'SHAREDLIBPREFIX=libfp'#010+
+  'SHAREDLIBPREFIX=libfp'#010,
   'STATICLIBPREFIX=libp'#010+
   'IMPORTLIBPREFIX=libimp'#010+
   'RSTEXT=.rst'#010+
@@ -945,9 +959,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '#DEBUGSYMEXT #for debugger symbol files, define only for targets which'+
   ' has this'#010+
   #010+
-  '# Go','32v1'#010+
+  '# Go32v1'#010+
   'ifeq ($(OS_TARGET),go32v1)'#010+
-  'STATICLIBPREFIX='#010+
+  'STATICLIBPREFIX','='#010+
   'SHORTSUFFIX=v1'#010+
   'endif'#010+
   #010+
@@ -963,9 +977,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'STATICLIBPREFIX='#010+
   'OEXT=.obj'#010+
   'ASMEXT=.asm'#010+
-  'S','HAREDLIBEXT=.dll'#010+
+  'SHAREDLIBEXT=.dll'#010+
   'SHORTSUFFIX=wat'#010+
-  'IMPORTLIBPREFIX='#010+
+  'IMPORTLIBPREFI','X='#010+
   'endif'#010+
   #010+
   '# Android native'#010+
@@ -980,13 +994,13 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Linux'#010+
   'ifeq ($(OS_TARGET),linux)'#010+
-  'BATCHEXT=.sh'#010,
+  'BATCHEXT=.sh'#010+
   'EXEEXT='#010+
   'HASSHAREDLIB=1'#010+
   'SHORTSUFFIX=lnx'#010+
   'endif'#010+
   #010+
-  '# DragonFly BSD'#010+
+  '#',' DragonFly BSD'#010+
   'ifeq ($(OS_TARGET),dragonfly)'#010+
   'BATCHEXT=.sh'#010+
   'EXEEXT='#010+
@@ -999,12 +1013,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'BATCHEXT=.sh'#010+
   'EXEEXT='#010+
   'HASSHAREDLIB=1'#010+
-  'SHORTSUFFIX=fbs'#010,
+  'SHORTSUFFIX=fbs'#010+
   'endif'#010+
   #010+
   '# NetBSD'#010+
   'ifeq ($(OS_TARGET),netbsd)'#010+
-  'BATCHEXT=.sh'#010+
+  'BATC','HEXT=.sh'#010+
   'EXEEXT='#010+
   'HASSHAREDLIB=1'#010+
   'SHORTSUFFIX=nbs'#010+
@@ -1020,12 +1034,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Win32'#010+
   'ifeq ($(OS_TARGET),win32)'#010+
-  'SHAREDL','IBEXT=.dll'#010+
+  'SHAREDLIBEXT=.dll'#010+
   'SHORTSUFFIX=w32'#010+
   'endif'#010+
   #010+
   '# OS/2'#010+
-  'ifeq ($(OS_TARGET),os2)'#010+
+  'ifeq (','$(OS_TARGET),os2)'#010+
   'BATCHEXT=.cmd'#010+
   'AOUTEXT=.out'#010+
   'STATICLIBPREFIX='#010+
@@ -1039,10 +1053,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifeq ($(OS_TARGET),emx)'#010+
   'BATCHEXT=.cmd'#010+
   'AOUTEXT=.out'#010+
-  'STATIC','LIBPREFIX='#010+
+  'STATICLIBPREFIX='#010+
   'SHAREDLIBEXT=.dll'#010+
   'SHORTSUFFIX=emx'#010+
-  'ECHO=echo'#010+
+  'EC','HO=echo'#010+
   'IMPORTLIBPREFIX='#010+
   'endif'#010+
   #010+
@@ -1057,11 +1071,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifeq ($(OS_TARGET),aros)'#010+
   'EXEEXT='#010+
   'SHAREDLIBEXT=.library'#010+
-  'SHORTSUFFIX=','aros'#010+
+  'SHORTSUFFIX=aros'#010+
   'endif'#010+
   #010+
   '# MorphOS'#010+
-  'ifeq ($(OS_TARGET),morphos)'#010+
+  'ifeq ($(OS_TARGET),morpho','s)'#010+
   'EXEEXT='#010+
   'SHAREDLIBEXT=.library'#010+
   'SHORTSUFFIX=mos'#010+
@@ -1077,12 +1091,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifeq ($(OS_TARGET),beos)'#010+
   'BATCHEXT=.sh'#010+
   'EXEEXT='#010+
-  'SHORTSUFFIX=be'#010,
+  'SHORTSUFFIX=be'#010+
   'endif'#010+
   #010+
   '# Haiku'#010+
   'ifeq ($(OS_TARGET),haiku)'#010+
-  'BATCHEXT=.sh'#010+
+  'BATCHE','XT=.sh'#010+
   'EXEEXT='#010+
   'SHORTSUFFIX=hai'#010+
   'endif'#010+
@@ -1099,11 +1113,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'BATCHEXT=.sh'#010+
   'EXEEXT='#010+
   'SHORTSUFFIX=qnx'#010+
-  'endif'#010,
+  'endif'#010+
   #010+
   '# Netware clib'#010+
   'ifeq ($(OS_TARGET),netware)'#010+
-  'EXEEXT=.nlm'#010+
+  'EXE','EXT=.nlm'#010+
   'STATICLIBPREFIX='#010+
   'SHORTSUFFIX=nw'#010+
   'IMPORTLIBPREFIX=imp'#010+
@@ -1118,10 +1132,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# MacOS'#010+
-  'i','feq ($(OS_TARGET),macos)'#010+
+  'ifeq ($(OS_TARGET),macos)'#010+
   'BATCHEXT='#010+
   'EXEEXT='#010+
-  'DEBUGSYMEXT=.xcoff'#010+
+  'DEBU','GSYMEXT=.xcoff'#010+
   'SHORTSUFFIX=mac'#010+
   'IMPORTLIBPREFIX=imp'#010+
   'endif'#010+
@@ -1133,12 +1147,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'HASSHAREDLIB=1'#010+
   'SHORTSUFFIX=dwn'#010+
   'EXEDBGEXT=.dSYM'#010+
-  'endif',#010+
+  'endif'#010+
   #010+
   '# gba'#010+
   'ifeq ($(OS_TARGET),gba)'#010+
   'EXEEXT=.gba'#010+
-  'SHAREDLIBEXT=.so'#010+
+  'SHA','REDLIBEXT=.so'#010+
   'SHORTSUFFIX=gba'#010+
   'endif'#010+
   #010+
@@ -1151,12 +1165,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# NativeNT'#010+
   'ifeq ($(OS_TARGET),NativeNT)'#010+
   'SHAREDLIBEXT=.dll'#010+
-  'SHORTSUFFIX=','nativent'#010+
+  'SHORTSUFFIX=nativent'#010+
   'endif'#010+
   #010+
   '# wii'#010+
   'ifeq ($(OS_TARGET),wii)'#010+
-  'EXEEXT=.dol'#010+
+  'E','XEEXT=.dol'#010+
   'SHAREDLIBEXT=.so'#010+
   'SHORTSUFFIX=wii'#010+
   'endif'#010+
@@ -1172,12 +1186,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Java'#010+
   'ifeq ($(OS_TARGET),java)'#010+
   'OEXT=.class'#010+
-  'ASMEXT=.','j'#010+
+  'ASMEXT=.j'#010+
   'SHAREDLIBEXT=.jar'#010+
   'SHORTSUFFIX=java'#010+
   'endif'#010+
   #010+
-  '# Android java'#010+
+  '# A','ndroid java'#010+
   'ifeq ($(CPU_TARGET),jvm)'#010+
   'ifeq ($(OS_TARGET),android)'#010+
   'OEXT=.class'#010+
@@ -1190,11 +1204,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# MS-DOS'#010+
   'ifeq ($(OS_TARGET),msdos)'#010+
   'STATICLIBPREFIX='#010+
-  'STA','TICLIBEXT=.a'#010+
+  'STATICLIBEXT=.a'#010+
   'SHORTSUFFIX=d16'#010+
   'endif'#010+
   #010+
-  '# Embedded'#010+
+  '# Embedded'#010,
   'ifeq ($(OS_TARGET),embedded)'#010+
   'ifeq ($(CPU_TARGET),i8086)'#010+
   'STATICLIBPREFIX='#010+
@@ -1208,20 +1222,20 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Win16'#010+
   'ifeq ($(OS_TARGET),win16)'#010+
   'STATICLIBPREFIX='#010+
-  'STATICL','IBEXT=.a'#010+
+  'STATICLIBEXT=.a'#010+
   'SHAREDLIBEXT=.dll'#010+
   'SHORTSUFFIX=w16'#010+
-  'endif'#010+
+  'endi','f'#010+
   #010+
   #010+
   '# For 8.3 limited OS'#039's the short suffixes'#010+
   '# Otherwise use the full source/target names'#010+
   'ifneq ($(findstring $(OS_SOURCE),$(LIMIT83fs)),)'#010+
   'FPCMADE=fpcmade.$(SHORTSUFFIX)'#010+
-  'ZIPSUFFIX=$(SHORTSUFFI','X)'#010+
+  'ZIPSUFFIX=$(SHORTSUFFIX)'#010+
   'ZIPCROSSPREFIX='#010+
   'ZIPSOURCESUFFIX=src'#010+
-  'ZIPEXAMPLESUFFIX=exm'#010+
+  'ZIPEXAMP','LESUFFIX=exm'#010+
   'else'#010+
   'FPCMADE=fpcmade.$(TARGETSUFFIX)'#010+
   'ZIPSOURCESUFFIX=.source'#010+
@@ -1230,19 +1244,19 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ZIPSUFFIX=.$(SOURCESUFFIX)'#010+
   'ZIPCROSSPREFIX=$(TARGETSUFFIX)-'#010+
   'else'#010+
-  'ZIPSUFFIX','=.$(TARGETSUFFIX)'#010+
+  'ZIPSUFFIX=.$(TARGETSUFFIX)'#010+
   'ZIPCROSSPREFIX='#010+
   'endif'#010+
   'endif'#010+
-  #010+
+  #010,
   '[defaulttools]'#010+
   '#####################################################################'#010+
   '# Default Tools'#010+
   '#####################################################################'#010+
   #010+
-  '# Names of the binuti','ls tools'#010+
+  '# Names of the binutils tools'#010+
   'ASNAME=$(BINUTILSPREFIX)as'#010+
-  'LDNAME=$(BINUTILSPREFIX)ld'#010+
+  'LDNAME=$(BI','NUTILSPREFIX)ld'#010+
   'ARNAME=$(BINUTILSPREFIX)ar'#010+
   'RCNAME=$(BINUTILSPREFIX)rc'#010+
   'NASMNAME=$(BINUTILSPREFIX)nasm'#010+
@@ -1250,9 +1264,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# assembler, redefine it if cross compiling'#010+
   'ifndef ASPROG'#010+
   'ifdef CROSSBINDIR'#010+
-  'ASPROG=$(CROSSB','INDIR)/$(ASNAME)$(SRCEXEEXT)'#010+
+  'ASPROG=$(CROSSBINDIR)/$(ASNAME)$(SRCEXEEXT)'#010+
   'else'#010+
-  'ASPROG=$(ASNAME)'#010+
+  'ASPROG=$(ASNA','ME)'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -1266,9 +1280,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# Resource compiler'#010+
-  'ifndef RCPROG',#010+
+  'ifndef RCPROG'#010+
   'ifdef CROSSBINDIR'#010+
-  'RCPROG=$(CROSSBINDIR)/$(RCNAME)$(SRCEXEEXT)'#010+
+  'RCPROG=$(CROSSBINDIR)/$(RCNA','ME)$(SRCEXEEXT)'#010+
   'else'#010+
   'RCPROG=$(RCNAME)'#010+
   'endif'#010+
@@ -1283,9 +1297,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   'endif'#010+
   #010+
-  '# NASM assembler, re','define it if cross compiling'#010+
+  '# NASM assembler, redefine it if cross compiling'#010+
   'ifndef NASMPROG'#010+
-  'ifdef CROSSBINDIR'#010+
+  'if','def CROSSBINDIR'#010+
   'NASMPROG=$(CROSSBINDIR)/$(NASMNAME)$(SRCEXEEXT)'#010+
   'else'#010+
   'NASMPROG=$(NASMNAME)'#010+
@@ -1298,10 +1312,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'RC=$(RCPROG)'#010+
   'AR=$(ARPROG)'#010+
   'NASM=$(NASMPROG)'#010+
-  #010,
+  #010+
   '# ppas.bat / ppas.sh'#010+
   'ifdef inUnix'#010+
-  'PPAS=./ppas$(SRCBATCHEXT)'#010+
+  'PPAS=./ppas$(','SRCBATCHEXT)'#010+
   'else'#010+
   'PPAS=ppas$(SRCBATCHEXT)'#010+
   'endif'#010+
@@ -1316,14 +1330,14 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifdef DATE'#010+
   'DATESTR:=$(shell $(DATE) +%Y%m%d)'#010+
   'else'#010+
-  'DATESTR='#010,
+  'DATESTR='#010+
   'endif'#010+
   #010+
   '# Zip options'#010+
   'ZIPOPT=-9'#010+
   'ZIPEXT=.zip'#010+
   #010+
-  '# Tar options'#010+
+  '# T','ar options'#010+
   'ifeq ($(USETAR),bz2)'#010+
   'TAROPT=vj'#010+
   'TAREXT=.tar.bz2'#010+
@@ -1335,17 +1349,18 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '[command_begin]'#010+
   '#####################################################################'#010+
-  '# Compiler ','Command Line'#010+
-  '#####################################################################'#010+
+  '# Compiler Command Line'#010+
+  '##################################','##################################'+
+  '#'#010+
   #010+
   '# Load commandline OPTDEF and add FPC_CPU define, for compiling the'#010+
   '# compiler this needs to be turned off'#010+
   'ifndef NOCPUDEF'#010+
   'override FPCOPTDEF=$(ARCH)'#010+
-  'endif'#010,
+  'endif'#010+
   #010+
   #010+
-  '# Load commandline OPT and add target and unit dir to be sure'#010+
+  '# Load commandline OPT and add target and uni','t dir to be sure'#010+
   'ifneq ($(OS_TARGET),$(OS_SOURCE))'#010+
   'override FPCOPT+=-T$(OS_TARGET)'#010+
   'endif'#010+
@@ -1355,8 +1370,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   'ifeq ($(OS_SOURCE),openbsd)'#010+
-  'overr','ide FPCOPT+=-FD$(NEW_BINUTILS_PATH)'#010+
-  'override FPCMAKEOPT+=-FD$(NEW_BINUTILS_PATH)'#010+
+  'override FPCOPT+=-FD$(NEW_BINUTILS_PATH)'#010+
+  'override FP','CMAKEOPT+=-FD$(NEW_BINUTILS_PATH)'#010+
   'override FPMAKE_BUILD_OPT+=-FD$(NEW_BINUTILS_PATH)'#010+
   'endif'#010+
   #010+
@@ -1364,8 +1379,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifneq ($(BINUTILSPREFIX),)'#010+
   'override FPCOPT+=-XP$(BINUTILSPREFIX)'#010+
   'endif'#010+
-  'ifneq ($','(BINUTILSPREFIX),)'#010+
-  'override FPCOPT+=-Xr$(RLINKPATH)'#010+
+  'ifneq ($(BINUTILSPREFIX),)'#010+
+  'override FPCOPT+=-Xr$(RLINKP','ATH)'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -1374,19 +1389,19 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# it while compiling the fpmake file. (For example to build i386-freeb'+
   'sd'#010+
   '# with BINUTILSPREFIX=i386-)'#010+
-  'if','ndef CROSSCOMPILE'#010+
+  'ifndef CROSSCOMPILE'#010+
   'ifneq ($(BINUTILSPREFIX),)'#010+
-  'override FPCMAKEOPT+=-XP$(BINUTILSPREFIX)'#010+
+  'ov','erride FPCMAKEOPT+=-XP$(BINUTILSPREFIX)'#010+
   'override FPMAKE_BUILD_OPT+=-XP$(BINUTILSPREFIX)'#010+
   'endif'#010+
   'endif'#010+
   #010+
   '# User dirs should be first, so they are looked at first'#010+
   'ifdef UNITDIR'#010+
-  'override FPCOPT+=$(ad','dprefix -Fu,$(UNITDIR))'#010+
+  'override FPCOPT+=$(addprefix -Fu,$(UNITDIR))'#010+
   'endif'#010+
   'ifdef LIBDIR'#010+
-  'override FPCOPT+=$(addprefix -Fl,$(LIBDIR))'#010+
+  'over','ride FPCOPT+=$(addprefix -Fl,$(LIBDIR))'#010+
   'endif'#010+
   'ifdef OBJDIR'#010+
   'override FPCOPT+=$(addprefix -Fo,$(OBJDIR))'#010+
@@ -1396,11 +1411,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# Smartlinking'#010+
-  'ifdef',' LINKSMART'#010+
+  'ifdef LINKSMART'#010+
   'override FPCOPT+=-XX'#010+
   'endif'#010+
   #010+
-  '# Smartlinking creation'#010+
+  '# Smartl','inking creation'#010+
   'ifdef CREATESMART'#010+
   'override FPCOPT+=-CX'#010+
   'endif'#010+
@@ -1412,10 +1427,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# Release mode'#010+
-  '# (strip, optimize and don'#039't load fpc.cfg)',#010+
+  '# (strip, optimize and don'#039't load fpc.cfg)'#010+
   'ifdef RELEASE'#010+
   'FPCCPUOPT:=-O2'#010+
-  'override FPCOPT+=-Ur -Xs $(FPCCPUOPT) -n'#010+
+  'override FPCOPT+=','-Ur -Xs $(FPCCPUOPT) -n'#010+
   'override FPCOPTDEF+=RELEASE'#010+
   'endif'#010+
   #010+
@@ -1429,10 +1444,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'override FPCOPT+=-O2'#010+
   'endif'#010+
   #010+
-  '# Verbose settings (warning,not','e,info)'#010+
+  '# Verbose settings (warning,note,info)'#010+
   'ifdef VERBOSE'#010+
   'override FPCOPT+=-vwni'#010+
-  'endif'#010+
+  'en','dif'#010+
   #010+
   '# Needed compiler options'#010+
   'ifdef COMPILER_OPTIONS'#010+
@@ -1441,56 +1456,56 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifdef COMPILER_UNITDIR'#010+
   'override FPCOPT+=$(addprefix -Fu,$(COMPILER_UNITDIR))'#010+
   'endif'#010+
-  'ifdef COMPILE','R_LIBRARYDIR'#010+
-  'override FPCOPT+=$(addprefix -Fl,$(COMPILER_LIBRARYDIR))'#010+
+  'ifdef COMPILER_LIBRARYDIR'#010+
+  'override FPCOPT+=$(addprefix -Fl,$','(COMPILER_LIBRARYDIR))'#010+
   'endif'#010+
   'ifdef COMPILER_OBJECTDIR'#010+
   'override FPCOPT+=$(addprefix -Fo,$(COMPILER_OBJECTDIR))'#010+
   'endif'#010+
   'ifdef COMPILER_INCLUDEDIR'#010+
-  'override FPCOPT+=$(addprefix -Fi,$(COMPILER_INCLUDE','DIR))'#010+
+  'override FPCOPT+=$(addprefix -Fi,$(COMPILER_INCLUDEDIR))'#010+
   'endif'#010+
   #010+
   '# Cross compiler utils'#010+
-  'ifdef CROSSBINDIR'#010+
+  'ifdef CROSS','BINDIR'#010+
   'override FPCOPT+=-FD$(CROSSBINDIR)'#010+
   'endif'#010+
   #010+
   '# Target dirs and the prefix to use for clean/install'#010+
   'ifdef COMPILER_TARGETDIR'#010+
   'override FPCOPT+=-FE$(COMPILER_TARGETDIR)'#010+
-  'ifeq ($(COMPILER_TARGET','DIR),.)'#010+
+  'ifeq ($(COMPILER_TARGETDIR),.)'#010+
   'override TARGETDIRPREFIX='#010+
   'else'#010+
-  'override TARGETDIRPREFIX=$(COMPILER_TARGETDIR)/'#010+
+  'override',' TARGETDIRPREFIX=$(COMPILER_TARGETDIR)/'#010+
   'endif'#010+
   'endif'#010+
   #010+
   '# Unit target dir (default is units/<cpu>-<os>/'#010+
   'ifdef COMPILER_UNITTARGETDIR'#010+
   'override FPCOPT+=-FU$(COMPILER_UNITTARGETDIR)'#010+
-  'ifeq ($(COMPILER_','UNITTARGETDIR),.)'#010+
-  'override UNITTARGETDIRPREFIX='#010+
+  'ifeq ($(COMPILER_UNITTARGETDIR),.)'#010+
+  'override UNITTARGETDIRPREFIX=',#010+
   'else'#010+
   'override UNITTARGETDIRPREFIX=$(COMPILER_UNITTARGETDIR)/'#010+
   'endif'#010+
   'else'#010+
   'ifdef COMPILER_TARGETDIR'#010+
   'override COMPILER_UNITTARGETDIR=$(COMPILER_TARGETDIR)'#010+
-  'override UNITTARGETDIRPREFIX=$(TARGETDIRP','REFIX)'#010+
+  'override UNITTARGETDIRPREFIX=$(TARGETDIRPREFIX)'#010+
   'endif'#010+
   'endif'#010+
   #010+
   'ifdef CREATESHARED'#010+
-  'override FPCOPT+=-Cg'#010+
+  'override',' FPCOPT+=-Cg'#010+
   'endif'#010+
   #010+
   '# create always pic'#039'ed code on x86_64, mips and mipsel'#010+
   '# on unix-like systems'#010+
   'ifneq ($(findstring $(OS_TARGET),dragonfly freebsd openbsd netbsd linu'+
   'x solaris),)'#010+
-  'ifneq ($(fin','dstring $(CPU_TARGET),x86_64 mips mipsel),)'#010+
-  'override FPCOPT+=-Cg'#010+
+  'ifneq ($(findstring $(CPU_TARGET),x86_64 mips mipsel),)'#010+
+  'ove','rride FPCOPT+=-Cg'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -1502,10 +1517,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '[command_libc]'#010+
   '# Add GCC lib path if asked'#010+
   'ifdef GCCLIBDIR'#010+
-  'override FPCOPT+=-Fl$(GCCLIBDI','R)'#010+
+  'override FPCOPT+=-Fl$(GCCLIBDIR)'#010+
   'override FPCMAKEOPT+=-Fl$(GCCLIBDIR)'#010+
   'endif'#010+
-  'ifdef OTHERLIBDIR'#010+
+  'i','fdef OTHERLIBDIR'#010+
   'override FPCOPT+=$(addprefix -Fl,$(OTHERLIBDIR))'#010+
   'endif'#010+
   #010+
@@ -1516,7 +1531,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'override FPCOPT+=$(OPT)'#010+
   'endif'#010+
   #010+
-  '# Override o','ptions to compile the fpmake-binary with command-line op'+
+  '# Override options to compile the fpmake-binary with comman','d-line op'+
   'tions provided in FPMAKEBUILDOPT'#010+
   'ifdef FPMAKEBUILDOPT'#010+
   'override FPMAKE_BUILD_OPT+=$(FPMAKEBUILDOPT)'#010+
@@ -1524,10 +1539,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '# Add defines from FPCOPTDEF to FPCOPT'#010+
   'ifdef FPCOPTDEF'#010+
-  'override FPCOPT+=$(addp','refix -d,$(FPCOPTDEF))'#010+
+  'override FPCOPT+=$(addprefix -d,$(FPCOPTDEF))'#010+
   'endif'#010+
   #010+
-  '# Was a config file specified ?'#010+
+  '# Was a config fi','le specified ?'#010+
   'ifdef CFGFILE'#010+
   'override FPCOPT+=@$(CFGFILE)'#010+
   'endif'#010+
@@ -1536,10 +1551,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifdef USEENV'#010+
   'override FPCEXTCMD:=$(FPCOPT)'#010+
   'override FPCOPT:=!FPCEXTCMD'#010+
-  'export',' FPCEXTCMD'#010+
+  'export FPCEXTCMD'#010+
   'endif'#010+
   #010+
-  'override AFULL_TARGET=$(CPU_TARGET)-$(OS_TARGET)'#010+
+  'override AFULL_TARGET=$(CPU_T','ARGET)-$(OS_TARGET)'#010+
   'override AFULL_SOURCE=$(CPU_SOURCE)-$(OS_SOURCE)'#010+
   #010+
   'ifneq ($(AFULL_TARGET),$(AFULL_SOURCE))'#010+
@@ -1548,18 +1563,18 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   'ifdef ACROSSCOMPILE'#010+
   'override FPCOPT+=$(CROSSOPT)'#010+
-  'en','dif'#010+
+  'endif'#010+
   #010+
   '# Compiler commandline'#010+
-  'override COMPILER:=$(strip $(FPC) $(FPCOPT))'#010+
+  'override COMPILER:=','$(strip $(FPC) $(FPCOPT))'#010+
   #010+
   '# also call ppas if with command option -s'#010+
   '# but only if the FULL_SOURCE and FULL_TARGET are equal'#010+
   '# or if -sh is used'#010+
   'ifneq (,$(findstring -sh ,$(COMPILER)))'#010+
-  'UseEXEC','PPAS=1'#010+
+  'UseEXECPPAS=1'#010+
   'endif'#010+
-  'ifneq (,$(findstring -s ,$(COMPILER)))'#010+
+  'ifneq (,$(findstring -s ,$(COMPILE','R)))'#010+
   'ifeq ($(FULL_SOURCE),$(FULL_TARGET))'#010+
   'UseEXECPPAS=1'#010+
   'endif'#010+
@@ -1575,37 +1590,38 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   #010+
-  '[','loaderrules]'#010+
-  '#####################################################################'#010+
+  '[loaderrules]'#010+
+  '##################################','##################################'+
+  '#'#010+
   '# Loaders'#010+
   '#####################################################################'#010+
   #010+
   '.PHONY: fpc_loaders'#010+
   #010+
   'ifneq ($(TARGET_LOADERS),)'#010+
-  'override ALLTARGET+=fpc_load','ers'#010+
+  'override ALLTARGET+=fpc_loaders'#010+
   'override CLEANTARGET+=fpc_loaders_clean'#010+
-  'override INSTALLTARGET+=fpc_loaders_install'#010+
+  'ove','rride INSTALLTARGET+=fpc_loaders_install'#010+
   #010+
   'override LOADEROFILES:=$(addsuffix $(OEXT),$(TARGET_LOADERS))'#010+
   'endif'#010+
   #010+
   '%$(OEXT): %$(LOADEREXT)'#010+
   'ifdef COMPILER_UNITTARGETDIR'#010+
-  '        $(AS) -o $(COMPILER_U','NITTARGETDIR)/$*$(OEXT) $<'#010+
+  '        $(AS) -o $(COMPILER_UNITTARGETDIR)/$*$(OEXT) $<'#010+
   'else'#010+
-  '        $(AS) -o $*$(OEXT) $<'#010+
+  '        $(AS) -','o $*$(OEXT) $<'#010+
   'endif'#010+
   #010+
   'fpc_loaders: $(COMPILER_UNITTARGETDIR) $(LOADEROFILES)'#010+
   #010+
   'fpc_loaders_clean:'#010+
   'ifdef COMPILER_UNITTARGETDIR'#010+
-  '        -$(DEL) $(addprefix $(COMPILER_UNITTARGETDIR)/,$(LOADEROFIL','E'+
-  'S))'#010+
+  '        -$(DEL) $(addprefix $(COMPILER_UNITTARGETDIR)/,$(LOADEROFILES)'+
+  ')'#010+
   'else'#010+
   '        -$(DEL) $(LOADEROFILES)'#010+
-  'endif'#010+
+  'endif',#010+
   #010+
   'fpc_loaders_install:'#010+
   '        $(MKDIR) $(INSTALL_UNITDIR)'#010+
@@ -1613,7 +1629,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        $(INSTALL) $(addprefix $(COMPILER_UNITTARGETDIR)/,$(LOADEROFIL'+
   'ES)) $(INSTALL_UNITDIR)'#010+
   'else'#010+
-  '      ','  $(INSTALL) $(LOADEROFILES) $(INSTALL_UNITDIR)'#010+
+  '        $(INSTALL) $(LOADEROFILES) $(INSTALL_UNITDIR)',#010+
   'endif'#010+
   #010+
   #010+
@@ -1624,42 +1640,42 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '.PHONY: fpc_units'#010+
   #010+
-  'ifne','q ($(TARGET_UNITS)$(TARGET_IMPLICITUNITS),)'#010+
-  'override ALLTARGET+=fpc_units'#010+
+  'ifneq ($(TARGET_UNITS)$(TARGET_IMPLICITUNITS),)'#010+
+  'ove','rride ALLTARGET+=fpc_units'#010+
   #010+
   'override UNITPPUFILES=$(addsuffix $(PPUEXT),$(TARGET_UNITS))'#010+
   'override IMPLICITUNITPPUFILES=$(addsuffix $(PPUEXT),$(TARGET_IMPLICITU'+
   'NITS))'#010+
-  'override INSTALLPPUFILES+=$','(UNITPPUFILES) $(IMPLICITUNITPPUFILES)'#010+
-  'override CLEANPPUFILES+=$(UNITPPUFILES) $(IMPLICITUNITPPUFILES)'#010+
+  'override INSTALLPPUFILES+=$(UNITPPUFILES) $(IMPLICITUNITPPUFILES)'#010+
+  'override',' CLEANPPUFILES+=$(UNITPPUFILES) $(IMPLICITUNITPPUFILES)'#010+
   'endif'#010+
   #010+
   'fpc_units: $(COMPILER_UNITTARGETDIR) $(UNITPPUFILES)'#010+
   #010+
   #010+
   '[exerules]'#010+
-  '################################################################','####'+
-  '#'#010+
-  '# Exes'#010+
   '#####################################################################'#010+
+  '# Exes'#010+
+  '##################################','##################################'+
+  '#'#010+
   #010+
   '.PHONY: fpc_exes'#010+
   #010+
   '# Programs are not needed for a cross installation'#010+
   'ifndef CROSSINSTALL'#010+
   'ifneq ($(TARGET_PROGRAMS),)'#010+
-  'override EXEFILES=$(addsuffix $(EXEEXT)',',$(TARGET_PROGRAMS))'#010+
-  'override EXEOFILES:=$(addsuffix $(OEXT),$(TARGET_PROGRAMS)) $(addsuffi'+
-  'x $(LTOEXT),$(TARGET_PROGRAMS))$(addprefix $(STATICLIBPREFIX),$(addsuf'+
-  'fix $(STATICLIBEXT),$(TARGET_PROGRAMS))) $(addprefix $(IMPORTLIBPREFIX'+
-  '),$(addsu','ffix $(STATICLIBEXT),$(TARGET_PROGRAMS)))'#010+
-  'override EXEDBGFILES:=$(addsuffix $(EXEDBGEXT),$(TARGET_PROGRAMS))'#010+
+  'override EXEFILES=$(addsuffix $(EXEEXT),$(TARGET_PROGRAMS))'#010+
+  'override EXEOFILES:=$(adds','uffix $(OEXT),$(TARGET_PROGRAMS)) $(addsuf'+
+  'fix $(LTOEXT),$(TARGET_PROGRAMS))$(addprefix $(STATICLIBPREFIX),$(adds'+
+  'uffix $(STATICLIBEXT),$(TARGET_PROGRAMS))) $(addprefix $(IMPORTLIBPREF'+
+  'IX),$(addsuffix $(STATICLIBEXT),$(TARGET_PROGRAMS)))'#010+
+  'overr','ide EXEDBGFILES:=$(addsuffix $(EXEDBGEXT),$(TARGET_PROGRAMS))'#010+
   #010+
   'override ALLTARGET+=fpc_exes'#010+
   'override INSTALLEXEFILES+=$(EXEFILES)'#010+
   'override CLEANEXEFILES+=$(EXEFILES) $(EXEOFILES)'#010+
-  'override CLEAN','EXEDBGFILES+=$(EXEDBGFILES)'#010+
-  'ifeq ($(OS_TARGET),os2)'#010+
+  'override CLEANEXEDBGFILES+=$(EXEDBGFILES)'#010+
+  'ifeq ($(OS_TARGET),','os2)'#010+
   'override CLEANEXEFILES+=$(addsuffix $(AOUTEXT),$(TARGET_PROGRAMS))'#010+
   'endif'#010+
   'ifeq ($(OS_TARGET),emx)'#010+
@@ -1668,7 +1684,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   'endif'#010+
   #010+
-  'fpc_e','xes: $(COMPILER_TARGETDIR) $(COMPILER_UNITTARGETDIR) $(EXEFILES'+
+  'fpc_exes: $(COMPILER_TARGETDIR) $(COMPILER_UNITTARGE','TDIR) $(EXEFILES'+
   ')'#010+
   #010+
   #010+
@@ -1677,8 +1693,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Resource strings'#010+
   '#####################################################################'#010+
   #010+
-  'if','def TARGET_RSTS'#010+
-  'override RSTFILES=$(addsuffix $(RSTEXT),$(TARGET_RSTS))'#010+
+  'ifdef TARGET_RSTS'#010+
+  'override RSTFILES=$(addsuffix $','(RSTEXT),$(TARGET_RSTS))'#010+
   #010+
   'override CLEANRSTFILES+=$(RSTFILES)'#010+
   'endif'#010+
@@ -1687,34 +1703,33 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '[examplerules]'#010+
   '#####################################################################'#010+
   '# Examples'#010+
-  '###########################','#########################################'+
-  '#'#010+
+  '#####################################################################'#010+
   #010+
-  '.PHONY: fpc_examples'#010+
+  '.PH','ONY: fpc_examples'#010+
   #010+
   'ifneq ($(TARGET_EXAMPLES),)'#010+
   'HASEXAMPLES=1'#010+
   'override EXAMPLESOURCEFILES=$(wildcard $(addsuffix .pp,$(TARGET_EXAMPL'+
-  'ES)) $(addsuffix .pas,$(TARGET_EXAMPLES)) $(addsuffix .lpr,$(T','ARGET_'+
-  'EXAMPLES)) $(addsuffix .dpr,$(TARGET_EXAMPLES)))'#010+
+  'ES)) $(addsuffix .pas,$(TARGET_EXAMPLES)) $(addsuffix .lpr,$(TARGET_EX'+
+  'AMPLES)) $(addsuffix .dpr,$(TARGET_EXAM','PLES)))'#010+
   'override EXAMPLEFILES:=$(addsuffix $(EXEEXT),$(TARGET_EXAMPLES))'#010+
   'override EXAMPLEOFILES:=$(addsuffix $(OEXT),$(TARGET_EXAMPLES)) $(adds'+
-  'uffix $(LTOEXT),$(TARGET_EXAMPLES)) $(addprefix $(','STATICLIBPREFIX),$'+
-  '(addsuffix $(STATICLIBEXT),$(TARGET_EXAMPLES))) $(addprefix $(IMPORTLI'+
+  'uffix $(LTOEXT),$(TARGET_EXAMPLES)) $(addprefix $(STATICLIBPREFIX),$(a'+
+  'ddsuffix $(STATICLIBEXT),$(','TARGET_EXAMPLES))) $(addprefix $(IMPORTLI'+
   'BPREFIX),$(addsuffix $(STATICLIBEXT),$(TARGET_EXAMPLES)))'#010+
   'override EXAMPLEDBGFILES:=$(addsuffix $(EXEDBGEXT),$(TARGET_EXAMPLES))'+
   #010+
   #010+
-  'override CLEANEXEFILES','+=$(EXAMPLEFILES) $(EXAMPLEOFILES)'#010+
-  'override CLEANEXEDBGFILES+=$(EXAMPLEDBGFILES)'#010+
+  'override CLEANEXEFILES+=$(EXAMPLEFILES) $(EXAMPLEOFILES)'#010+
+  'override CLE','ANEXEDBGFILES+=$(EXAMPLEDBGFILES)'#010+
   'ifeq ($(OS_TARGET),os2)'#010+
   'override CLEANEXEFILES+=$(addsuffix $(AOUTEXT),$(TARGET_EXAMPLES))'#010+
   'endif'#010+
   'ifeq ($(OS_TARGET),emx)'#010+
-  'override CLEANEXEFILES+=$(addsuffix $(','AOUTEXT),$(TARGET_EXAMPLES))'#010+
+  'override CLEANEXEFILES+=$(addsuffix $(AOUTEXT),$(TARGET_EXAMPLES))'#010+
   'endif'#010+
   'endif'#010+
-  'ifneq ($(TARGET_EXAMPLEDIRS),)'#010+
+  'ifneq ','($(TARGET_EXAMPLEDIRS),)'#010+
   'HASEXAMPLES=1'#010+
   'endif'#010+
   #010+
@@ -1723,19 +1738,19 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   #010+
   '[compilerules]'#010+
-  '########################################################','############'+
-  '#'#010+
-  '# General compile rules'#010+
   '#####################################################################'#010+
+  '# General compile rules'#010+
+  '#########','###########################################################'+
+  '#'#010+
   #010+
   '.PHONY: fpc_all fpc_smart fpc_debug fpc_release fpc_shared'#010+
   #010+
   '$(FPCMADE): $(ALLDEPENDENCIES) $(ALLTARGET)'#010+
-  '        @$(ECHOREDIR) Compi','led > $(FPCMADE)'#010+
+  '        @$(ECHOREDIR) Compiled > $(FPCMADE)'#010+
   #010+
   'fpc_all: $(FPCMADE)'#010+
   #010+
-  'fpc_smart:'#010+
+  'fpc_smar','t:'#010+
   '        $(MAKE) all LINKSMART=1 CREATESMART=1'#010+
   #010+
   'fpc_debug:'#010+
@@ -1744,11 +1759,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'fpc_release:'#010+
   '        $(MAKE) all RELEASE=1'#010+
   #010+
-  '# General compile rules, available for both possible .pp an','d .pas ex'+
-  'tensions'#010+
+  '# General compile rules, available for both possible .pp and .pas exte'+
+  'nsions'#010+
   #010+
-  '.SUFFIXES: $(EXEEXT) $(PPUEXT) $(OEXT) $(LTOEXT) .pas .lpr .dpr .pp .r'+
-  'c .res'#010+
+  '.SUFFIXES: $(EXEEXT) $(PPUEX','T) $(OEXT) $(LTOEXT) .pas .lpr .dpr .pp '+
+  '.rc .res'#010+
   #010+
   '$(COMPILER_UNITTARGETDIR):'#010+
   '        $(MKDIRTREE) $(COMPILER_UNITTARGETDIR)'#010+
@@ -1756,9 +1771,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '$(COMPILER_TARGETDIR):'#010+
   '        $(MKDIRTREE) $(COMPILER_TARGETDIR)'#010+
   #010+
-  '%','$(PPUEXT): %.pp'#010+
+  '%$(PPUEXT): %.pp'#010+
   '        $(COMPILER) $<'#010+
-  '        $(EXECPPAS)'#010+
+  '        ','$(EXECPPAS)'#010+
   #010+
   '%$(PPUEXT): %.pas'#010+
   '        $(COMPILER) $<'#010+
@@ -1770,11 +1785,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   '%$(EXEEXT): %.pas'#010+
   '        $(COMPILER) $<'#010+
-  '        $(EXECPP','AS)'#010+
+  '        $(EXECPPAS)'#010+
   #010+
   '%$(EXEEXT): %.lpr'#010+
   '        $(COMPILER) $<'#010+
-  '        $(EXECPPAS)'#010+
+  ' ','       $(EXECPPAS)'#010+
   #010+
   '%$(EXEEXT): %.dpr'#010+
   '        $(COMPILER) $<'#010+
@@ -1784,19 +1799,19 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        windres -i $< -o $@'#010+
   #010+
   '# Search paths for .ppu, .pp, .pas, .lpr, .dpr'#010+
-  'vpath %.pp $(COMPILER_S','OURCEDIR) $(COMPILER_INCLUDEDIR)'#010+
-  'vpath %.pas $(COMPILER_SOURCEDIR) $(COMPILER_INCLUDEDIR)'#010+
+  'vpath %.pp $(COMPILER_SOURCEDIR) $(COMPILER_INCLUDEDIR)'#010+
+  'vpath %.pas $(','COMPILER_SOURCEDIR) $(COMPILER_INCLUDEDIR)'#010+
   'vpath %.lpr $(COMPILER_SOURCEDIR) $(COMPILER_INCLUDEDIR)'#010+
   'vpath %.dpr $(COMPILER_SOURCEDIR) $(COMPILER_INCLUDEDIR)'#010+
   'vpath %.inc $(COMPILER_INCLUDEDIR)'#010+
-  'v','path %$(OEXT) $(COMPILER_UNITTARGETDIR)'#010+
-  'vpath %$(LTOEXT) $(COMPILER_UNITTARGETDIR)'#010+
+  'vpath %$(OEXT) $(COMPILER_UNITTARGETDIR)'#010+
+  'vpath %','$(LTOEXT) $(COMPILER_UNITTARGETDIR)'#010+
   'vpath %$(PPUEXT) $(COMPILER_UNITTARGETDIR)'#010+
   #010+
   '[sharedrules]'#010+
   '#####################################################################'#010+
   '# Library'#010+
-  '###################','#################################################'+
+  '##################################################################','##'+
   '#'#010+
   #010+
   '.PHONY: fpc_shared'#010+
@@ -1809,26 +1824,26 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   'ifndef SHARED_LIBNAME'#010+
   'SHARED_LIBNAME=$(PACKAGE_NAME)'#010+
-  'endif'#010,
+  'endif'#010+
   #010+
   'ifndef SHARED_FULLNAME'#010+
-  'SHARED_FULLNAME=$(SHAREDLIBPREFIX)$(SHARED_LIBNAME)-$(SHARED_LIBVERSIO'+
-  'N)$(SHAREDLIBEXT)'#010+
+  'SHARED_FULLNAME=$(SHARE','DLIBPREFIX)$(SHARED_LIBNAME)-$(SHARED_LIBVERS'+
+  'ION)$(SHAREDLIBEXT)'#010+
   'endif'#010+
   #010+
   '# Default sharedlib units are all unit objects'#010+
   'ifndef SHARED_LIBUNITS'#010+
-  'SHARED_LIBUNITS:=$(TARGET_UNITS) $(TARGET_IMPLICITU','NITS)'#010+
-  'override SHARED_LIBUNITS:=$(filter-out $(INSTALL_BUILDUNIT),$(SHARED_L'+
-  'IBUNITS))'#010+
+  'SHARED_LIBUNITS:=$(TARGET_UNITS) $(TARGET_IMPLICITUNITS)'#010+
+  'override SHARED_LIBUNITS:=$(filter-out $(','INSTALL_BUILDUNIT),$(SHARED'+
+  '_LIBUNITS))'#010+
   'endif'#010+
   #010+
   'fpc_shared:'#010+
   'ifdef HASSHAREDLIB'#010+
   '        $(MAKE) all CREATESHARED=1 LINKSHARED=1 CREATESMART=1'#010+
   'ifneq ($(SHARED_BUILD),n)'#010+
-  '        $(PPUMOVE) -q $(SHAR','ED_LIBUNITS) -i$(COMPILER_UNITTARGETDIR)'+
-  ' -o$(SHARED_FULLNAME) -d$(COMPILER_UNITTARGETDIR) -P$(BINUTILSPREFIX)'#010+
+  '        $(PPUMOVE) -q $(SHARED_LIBUNITS) -i$(COMPILER_UNITTARGETDIR) -'+
+  'o$(SH','ARED_FULLNAME) -d$(COMPILER_UNITTARGETDIR) -P$(BINUTILSPREFIX)'#010+
   'endif'#010+
   'else'#010+
   '        @$(ECHO) Shared Libraries not supported'#010+
@@ -1836,8 +1851,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   'fpc_shared_install:'#010+
   'ifneq ($(SHARED_BUILD),n)'#010+
-  'ifneq ($(SHARED_LI','BUNITS),)'#010+
-  'ifneq ($(wildcard $(COMPILER_UNITTARGETDIR)/$(SHARED_FULLNAME)),)'#010+
+  'ifneq ($(SHARED_LIBUNITS),)'#010+
+  'ifneq ($(wildcard $(COMPILER_UNITTARG','ETDIR)/$(SHARED_FULLNAME)),)'#010+
   '        $(INSTALL) $(COMPILER_UNITTARGETDIR)/$(SHARED_FULLNAME) $(INST'+
   'ALL_SHAREDDIR)'#010+
   'endif'#010+
@@ -1845,73 +1860,73 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '[installrules]'#010+
-  '#############################################','#######################'+
-  '#'#010+
-  '# Install rules'#010+
   '#####################################################################'#010+
+  '# Install rules'#010+
+  '######','##############################################################'+
+  '#'#010+
   #010+
   '.PHONY: fpc_install fpc_sourceinstall fpc_exampleinstall'#010+
   #010+
   'ifdef INSTALL_UNITS'#010+
-  'override INSTALLPPUFILES+=$(addsuffix $(PPUEXT),$(','INSTALL_UNITS))'#010+
+  'override INSTALLPPUFILES+=$(addsuffix $(PPUEXT),$(INSTALL_UNITS))'#010+
   'endif'#010+
   #010+
-  'ifdef INSTALL_BUILDUNIT'#010+
+  'ifdef INSTALL_BUILDUNIT'#010,
   'override INSTALLPPUFILES:=$(filter-out $(INSTALL_BUILDUNIT)$(PPUEXT),$'+
   '(INSTALLPPUFILES))'#010+
   'endif'#010+
   #010+
   'ifdef INSTALLPPUFILES'#010+
   '# Avoid getting the same name twice as some install EXE fail'#010+
-  '# in this case',', happends for instance for OS/2 target'#010+
-  'ifneq ($(IMPORTLIBPREFIX)-$(STATICLIBEXT),$(STATICLIBPREFIX)-$(STATICL'+
-  'IBEXT))'#010+
+  '# in this case, happends for instance for OS/2 target'#010+
+  'ifneq (','$(IMPORTLIBPREFIX)-$(STATICLIBEXT),$(STATICLIBPREFIX)-$(STATI'+
+  'CLIBEXT))'#010+
   'override INSTALLPPULINKFILES:=$(subst $(PPUEXT),$(OEXT),$(INSTALLPPUFI'+
-  'LES)) $(subst $(PPUEXT),$(LTOEXT),$(INSTALLPPUFILES)',') $(addprefix $('+
-  'STATICLIBPREFIX),$(subst $(PPUEXT),$(STATICLIBEXT),$(INSTALLPPUFILES))'+
+  'LES)) $(subst $(PPUEXT),$(LTOEXT),$(INSTALLPPUFILES)) $(addprefix $(ST'+
+  'ATICLIBPREFIX),$(subst $(PPUE','XT),$(STATICLIBEXT),$(INSTALLPPUFILES))'+
   ') $(addprefix $(IMPORTLIBPREFIX),$(subst $(PPUEXT),$(STATICLIBEXT),$(I'+
   'NSTALLPPUFILES)))'#010+
   'else'#010+
-  'override INSTALLPPULINKFILES:=$(subst $(PPUEXT),$(OEXT),$(INS','TALLPPU'+
-  'FILES)) $(subst $(PPUEXT),$(LTOEXT),$(INSTALLPPUFILES)) $(addprefix $('+
+  'override INSTALLPPULINKFILES:=$(subst $(PPUEXT),$(OEXT),$(INSTALLPPUFI'+
+  'LES)) $(subst $(PPUEXT),$(LTOEXT),$(IN','STALLPPUFILES)) $(addprefix $('+
   'STATICLIBPREFIX),$(subst $(PPUEXT),$(STATICLIBEXT),$(INSTALLPPUFILES))'+
   ')'#010+
   'endif'#010+
   #010+
   'ifneq ($(UNITTARGETDIRPREFIX),)'#010+
-  'override INSTALLPPUFILENAMES:=$(notdir $(INSTALLPPUF','ILES))'#010+
-  'override INSTALLPPULINKFILENAMES:=$(notdir $(INSTALLPPULINKFILES))'#010+
+  'override INSTALLPPUFILENAMES:=$(notdir $(INSTALLPPUFILES))'#010+
+  'override INSTALLPPULINKFILENAMES:=$(notd','ir $(INSTALLPPULINKFILES))'#010+
   'override INSTALLPPUFILES=$(addprefix $(UNITTARGETDIRPREFIX),$(INSTALLP'+
   'PUFILENAMES))'#010+
   'override INSTALLPPULINKFILES=$(wildcard $(addprefix $(UNITTARGETDIRPRE'+
-  'FIX),$(INSTA','LLPPULINKFILENAMES)))'#010+
+  'FIX),$(INSTALLPPULINKFILENAMES)))'#010+
   'endif'#010+
-  '# Implicitly install Package.fpc'#010+
+  '# Implicitly instal','l Package.fpc'#010+
   'override INSTALL_CREATEPACKAGEFPC=1'#010+
   'endif'#010+
   #010+
   'ifdef INSTALLEXEFILES'#010+
   'ifneq ($(TARGETDIRPREFIX),)'#010+
   'override INSTALLEXEFILES:=$(addprefix $(TARGETDIRPREFIX),$(notdir $(IN'+
-  'STALLEXEFILES)))',#010+
+  'STALLEXEFILES)))'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  'fpc_install: all $(INSTALLTARGET)'#010+
+  'fpc_install: all $(INSTALLTARGET)',#010+
   'ifdef INSTALLEXEFILES'#010+
   '        $(MKDIR) $(INSTALL_BINDIR)'#010+
   '        $(INSTALLEXE) $(INSTALLEXEFILES) $(INSTALL_BINDIR)'#010+
   'endif'#010+
   'ifdef INSTALL_CREATEPACKAGEFPC'#010+
   'ifdef FPCMAKE'#010+
-  '# If the fpcpackage varia','ble is set then create and install Package.'+
-  'fpc,'#010+
+  '# If the fpcpackage variable is set then create and install Package.fp'+
+  'c,',#010+
   '# a safety check is done if Makefile.fpc is available'#010+
   'ifdef PACKAGE_VERSION'#010+
   'ifneq ($(wildcard Makefile.fpc),)'#010+
   '        $(FPCMAKE) -p -T$(CPU_TARGET)-$(OS_TARGET) Makefile.fpc'#010+
-  '        $(MKDIR) $','(INSTALL_UNITDIR)'#010+
-  '        $(INSTALL) Package.fpc $(INSTALL_UNITDIR)'#010+
+  '        $(MKDIR) $(INSTALL_UNITDIR)'#010+
+  '        $(INSTALL) Package.fp','c $(INSTALL_UNITDIR)'#010+
   'endif'#010+
   'endif'#010+
   'endif'#010+
@@ -1920,43 +1935,43 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        $(MKDIR) $(INSTALL_UNITDIR)'#010+
   '        $(INSTALL) $(INSTALLPPUFILES) $(INSTALL_UNITDIR)'#010+
   'ifneq ($(INSTALLPPULINKFILES),)'#010+
-  ' ','       $(INSTALL) $(INSTALLPPULINKFILES) $(INSTALL_UNITDIR)'#010+
+  '        $(INSTALL) $(INSTALLPPULINKFILES) $(INST','ALL_UNITDIR)'#010+
   'endif'#010+
   'ifneq ($(wildcard $(LIB_FULLNAME)),)'#010+
   '        $(MKDIR) $(INSTALL_LIBDIR)'#010+
   '        $(INSTALL) $(LIB_FULLNAME) $(INSTALL_LIBDIR)'#010+
   'ifdef inUnix'#010+
-  '        ln -sf $(LIB_FULLNAME) $(INS','TALL_LIBDIR)/$(LIB_NAME)'#010+
+  '        ln -sf $(LIB_FULLNAME) $(INSTALL_LIBDIR)/$(LIB_NAME)'#010+
   'endif'#010+
   'endif'#010+
   'endif'#010+
-  'ifdef INSTALL_FILES'#010+
+  'ifde','f INSTALL_FILES'#010+
   '        $(MKDIR) $(INSTALL_DATADIR)'#010+
   '        $(INSTALL) $(INSTALL_FILES) $(INSTALL_DATADIR)'#010+
   'endif'#010+
   #010+
   'fpc_sourceinstall: distclean'#010+
   '        $(MKDIR) $(INSTALL_SOURCEDIR)'#010+
-  '        $(CO','PYTREE) $(BASEDIR)/* $(INSTALL_SOURCEDIR)'#010+
+  '        $(COPYTREE) $(BASEDIR)/* $(INSTALL_SOURCEDIR)'#010+
   #010+
-  'fpc_exampleinstall: $(EXAMPLEINSTALLTARGET) $(addsuffix _distclean,$(T'+
-  'ARGET_EXAMPLEDIRS))'#010+
+  'fpc_','exampleinstall: $(EXAMPLEINSTALLTARGET) $(addsuffix _distclean,$'+
+  '(TARGET_EXAMPLEDIRS))'#010+
   'ifdef HASEXAMPLES'#010+
   '        $(MKDIR) $(INSTALL_EXAMPLEDIR)'#010+
   'endif'#010+
   'ifdef EXAMPLESOURCEFILES'#010+
-  '        $(COPY) $(E','XAMPLESOURCEFILES) $(INSTALL_EXAMPLEDIR)'#010+
-  'endif'#010+
+  '        $(COPY) $(EXAMPLESOURCEFILES) $(INSTALL_EXAMPLEDIR)'#010+
+  'endif'#010,
   'ifdef TARGET_EXAMPLEDIRS'#010+
   '        $(COPYTREE) $(addsuffix /*,$(TARGET_EXAMPLEDIRS)) $(INSTALL_EX'+
   'AMPLEDIR)'#010+
   'endif'#010+
   #010+
   '[distinstallrules]'#010+
-  '##############################################################','######'+
-  '#'#010+
-  '# Dist Install'#010+
   '#####################################################################'#010+
+  '# Dist Install'#010+
+  '########################','############################################'+
+  '#'#010+
   #010+
   '.PHONY: fpc_distinstall'#010+
   #010+
@@ -1964,17 +1979,16 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   #010+
   '[zipinstallrules]'#010+
-  '#############################################################','#######'+
-  '#'#010+
-  '# Zip'#010+
   '#####################################################################'#010+
+  '# Zip'#010+
+  '################################','####################################'+
+  '#'#010+
   #010+
   '.PHONY: fpc_zipinstall fpc_zipsourceinstall fpc_zipexampleinstall'#010+
   #010+
   '# Temporary path to pack a file, can only use a single deep'#010+
-  '# subdir, because the deltr','ee can'#039't see the whole tree to remove'+
-  #010+
-  'ifndef PACKDIR'#010+
+  '# subdir, because the deltree can'#039't see the whole tree to remove'#010+
+  'ifndef PA','CKDIR'#010+
   'ifndef inUnix'#010+
   'PACKDIR=$(BASEDIR)/../fpc-pack'#010+
   'else'#010+
@@ -1985,13 +1999,13 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Maybe create default zipname from packagename'#010+
   'ifndef ZIPNAME'#010+
   'ifdef DIST_ZIPNAME'#010+
-  'ZIPNAME=$(DIST_ZIPNA','ME)'#010+
+  'ZIPNAME=$(DIST_ZIPNAME)'#010+
   'else'#010+
   'ZIPNAME=$(PACKAGE_NAME)'#010+
   'endif'#010+
   'endif'#010+
   #010+
-  'ifndef FULLZIPNAME'#010+
+  'i','fndef FULLZIPNAME'#010+
   'FULLZIPNAME=$(ZIPCROSSPREFIX)$(ZIPPREFIX)$(ZIPNAME)$(ZIPSUFFIX)'#010+
   'endif'#010+
   #010+
@@ -2001,11 +2015,11 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ZIPTARGET=DIST_ZIPTARGET'#010+
   'else'#010+
   'ZIPTARGET=install'#010+
-  'endif'#010,
+  'endif'#010+
   'endif'#010+
   #010+
   '# Use tar by default under linux'#010+
-  'ifndef USEZIP'#010+
+  'ifndef ','USEZIP'#010+
   'ifdef inUnix'#010+
   'USETAR=1'#010+
   'endif'#010+
@@ -2017,23 +2031,24 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   #010+
   '# We need to be able to run in the current OS so fix'#010+
-  '# the path separat','or'#010+
+  '# the path separator'#010+
   'ifdef USEZIPWRAPPER'#010+
   'ZIPPATHSEP=$(PATHSEP)'#010+
-  'ZIPWRAPPER=$(subst /,$(PATHSEP),$(DIST_DESTDIR)/fpczip$(SRCBATCHEXT))'#010+
+  'ZI','PWRAPPER=$(subst /,$(PATHSEP),$(DIST_DESTDIR)/fpczip$(SRCBATCHEXT)'+
+  ')'#010+
   'else'#010+
   'ZIPPATHSEP=/'#010+
   'endif'#010+
   #010+
   '# Create commands to create the zip/tar file'#010+
   'ZIPCMD_CDPACK:=cd $(subst /,$(ZIPPATHSEP),$(PACKDIR))'#010+
-  'Z','IPCMD_CDBASE:=cd $(subst /,$(ZIPPATHSEP),$(BASEDIR))'#010+
+  'ZIPCMD_CDBASE:=cd $(subst /,$(ZIPPATHSEP),$(BASE','DIR))'#010+
   'ifdef USETAR'#010+
   'ZIPDESTFILE:=$(DIST_DESTDIR)/$(FULLZIPNAME)$(TAREXT)'#010+
   'ZIPCMD_ZIP:=$(TARPROG) c$(TAROPT)f $(ZIPDESTFILE) *'#010+
   'else'#010+
   'ZIPDESTFILE:=$(DIST_DESTDIR)/$(FULLZIPNAME)$(ZIPEXT)'#010+
-  'ZIPCMD_ZIP:','=$(subst /,$(ZIPPATHSEP),$(ZIPPROG)) -Dr $(ZIPOPT) $(ZIPD'+
+  'ZIPCMD_ZIP:=$(subst /,$(ZIPPATHSEP),$(ZIPPROG)) -Dr $(ZIPO','PT) $(ZIPD'+
   'ESTFILE) *'#010+
   'endif'#010+
   #010+
@@ -2041,14 +2056,14 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        $(MAKE) $(ZIPTARGET) INSTALL_PREFIX=$(PACKDIR) ZIPINSTALL=1'#010+
   '        $(MKDIR) $(DIST_DESTDIR)'#010+
   '        $(DEL) $(ZIPDESTFILE)'#010+
-  'ifdef USEZIPWRAPPE','R'#010+
-  '# Handle gecho separate as we need to espace \ with \\'#010+
+  'ifdef USEZIPWRAPPER'#010+
+  '# Handle gecho separate as we need to espace ','\ with \\'#010+
   'ifneq ($(ECHOREDIR),echo)'#010+
   '        $(ECHOREDIR) -e "$(subst \,\\,$(ZIPCMD_CDPACK))" > $(ZIPWRAPPE'+
   'R)'#010+
   '        $(ECHOREDIR) -e "$(subst \,\\,$(ZIPCMD_ZIP))" >> $(ZIPWRAPPER)'+
   #010+
-  '        $(ECH','OREDIR) -e "$(subst \,\\,$(ZIPCMD_CDBASE))" >> $(ZIPWRA'+
+  '        $(ECHOREDIR) -e "$(subst \,\\,$(ZIPCMD_CDBASE))" >> ','$(ZIPWRA'+
   'PPER)'#010+
   'else'#010+
   '        echo $(ZIPCMD_CDPACK) > $(ZIPWRAPPER)'#010+
@@ -2056,10 +2071,10 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        echo $(ZIPCMD_CDBASE) >> $(ZIPWRAPPER)'#010+
   'endif'#010+
   'ifdef inUnix'#010+
-  '        /bin/sh $(','ZIPWRAPPER)'#010+
+  '        /bin/sh $(ZIPWRAPPER)'#010+
   'else'#010+
   'ifdef RUNBATCH'#010+
-  '        $(RUNBATCH) $(ZIPWRAPPER)'#010+
+  '        $(RUNBA','TCH) $(ZIPWRAPPER)'#010+
   'else'#010+
   '        $(ZIPWRAPPER)'#010+
   'endif'#010+
@@ -2070,9 +2085,9 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'endif'#010+
   '        $(DELTREE) $(PACKDIR)'#010+
   #010+
-  'fpc_','zipsourceinstall:'#010+
-  '        $(MAKE) fpc_zipinstall ZIPTARGET=sourceinstall ZIPSUFFIX=$(ZIP'+
-  'SOURCESUFFIX)'#010+
+  'fpc_zipsourceinstall:'#010+
+  '        $(MAKE) fpc_zipinstal','l ZIPTARGET=sourceinstall ZIPSUFFIX=$(Z'+
+  'IPSOURCESUFFIX)'#010+
   #010+
   'fpc_zipexampleinstall:'#010+
   'ifdef HASEXAMPLES'#010+
@@ -2080,63 +2095,63 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'PEXAMPLESUFFIX)'#010+
   'endif'#010+
   #010+
-  'fpc','_zipdistinstall:'#010+
-  '        $(MAKE) fpc_zipinstall ZIPTARGET=distinstall'#010+
+  'fpc_zipdistinstall:'#010+
+  '        $(MAKE) fpc_zipinstall',' ZIPTARGET=distinstall'#010+
   #010+
   #010+
   '[cleanrules]'#010+
   '#####################################################################'#010+
   '# Clean rules'#010+
   '#####################################################################'#010+
-  #010,
+  #010+
   '.PHONY: fpc_clean fpc_cleanall fpc_distclean'#010+
   #010+
-  'ifdef EXEFILES'#010+
+  'i','fdef EXEFILES'#010+
   'override CLEANEXEFILES:=$(addprefix $(TARGETDIRPREFIX),$(CLEANEXEFILES'+
   '))'#010+
   'override CLEANEXEDBGFILES:=$(addprefix $(TARGETDIRPREFIX),$(CLEANEXEDB'+
   'GFILES))'#010+
   'endif'#010+
   #010+
-  'ifdef CLEAN_PROGRAMS',#010+
-  'override CLEANEXEFILES+=$(addprefix $(TARGETDIRPREFIX),$(addsuffix $(E'+
-  'XEEXT), $(CLEAN_PROGRAMS)))'#010+
+  'ifdef CLEAN_PROGRAMS'#010+
+  'override CLEANEXEFILES+=$(addprefix $(TARGETDI','RPREFIX),$(addsuffix $'+
+  '(EXEEXT), $(CLEAN_PROGRAMS)))'#010+
   'override CLEANEXEDBGFILES+=$(addprefix $(TARGETDIRPREFIX),$(addsuffix '+
   '$(EXEDBGEXT), $(CLEAN_PROGRAMS)))'#010+
   'endif'#010+
   #010+
   'ifdef CLEAN_UNITS'#010+
-  'override CLE','ANPPUFILES+=$(addsuffix $(PPUEXT),$(CLEAN_UNITS))'#010+
+  'override CLEANPPUFILES+=$(addsuffix $(PPUEXT),$(CLEAN_UNITS','))'#010+
   'endif'#010+
   #010+
   'ifdef CLEANPPUFILES'#010+
   'override CLEANPPULINKFILES:=$(subst $(PPUEXT),$(OEXT),$(CLEANPPUFILES)'+
   ') $(subst $(PPUEXT),$(LTOEXT),$(CLEANPPUFILES)) $(addprefix $(STATICLI'+
-  'BPREFIX),$(subst $(PPUE','XT),$(STATICLIBEXT),$(CLEANPPUFILES))) $(addp'+
-  'refix $(IMPORTLIBPREFIX),$(subst $(PPUEXT),$(STATICLIBEXT),$(CLEANPPUF'+
-  'ILES)))'#010+
+  'BPREFIX),$(subst $(PPUEXT),$(STATICLIBEXT),$(CLEANPPUFILES))) $(addpre',
+  'fix $(IMPORTLIBPREFIX),$(subst $(PPUEXT),$(STATICLIBEXT),$(CLEANPPUFIL'+
+  'ES)))'#010+
   'ifdef DEBUGSYMEXT'#010+
   'override CLEANPPULINKFILES+=$(subst $(PPUEXT),$(DEBUGSYMEXT),$(CLEANPP'+
   'UFILES))'#010+
   'endif'#010+
-  'override CLEAN','PPUFILENAMES:=$(CLEANPPUFILES)'#010+
-  'override CLEANPPUFILES=$(addprefix $(UNITTARGETDIRPREFIX),$(CLEANPPUFI'+
-  'LENAMES))'#010+
+  'override CLEANPPUFILENAMES:=$(CLEANPPUFILES)'#010+
+  'override CLEANPP','UFILES=$(addprefix $(UNITTARGETDIRPREFIX),$(CLEANPPU'+
+  'FILENAMES))'#010+
   'override CLEANPPULINKFILENAMES:=$(CLEANPPULINKFILES)'#010+
   'override CLEANPPULINKFILES=$(wildcard $(addprefix $(UNITTARGETDIRPREFI'+
-  'X),$(C','LEANPPULINKFILENAMES)))'#010+
+  'X),$(CLEANPPULINKFILENAMES)))'#010+
   'endif'#010+
   #010+
-  'fpc_clean: $(CLEANTARGET)'#010+
+  'fpc_clean: $(CLE','ANTARGET)'#010+
   'ifdef CLEANEXEFILES'#010+
   '        -$(DEL) $(CLEANEXEFILES)'#010+
   'endif'#010+
   '# DELTREE instead of DEL because on Mac OS X these are directories'#010+
   'ifdef CLEANEXEDBGFILES'#010+
-  '        -$(DELTREE) $(CLEANEXEDBGF','ILES)'#010+
+  '        -$(DELTREE) $(CLEANEXEDBGFILES)'#010+
   'endif'#010+
   'ifdef CLEANPPUFILES'#010+
-  '        -$(DEL) $(CLEANPPUFILES)'#010+
+  '        -$(DEL)',' $(CLEANPPUFILES)'#010+
   'endif'#010+
   'ifneq ($(CLEANPPULINKFILES),)'#010+
   '        -$(DEL) $(CLEANPPULINKFILES)'#010+
@@ -2144,25 +2159,25 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'ifdef CLEANRSTFILES'#010+
   '        -$(DEL) $(addprefix $(UNITTARGETDIRPREFIX),$(CLEANRSTFILES))'#010+
   'endif'#010+
-  'i','fdef CLEAN_FILES'#010+
-  '        -$(DEL) $(CLEAN_FILES)'#010+
+  'ifdef CLEAN_FILES'#010+
+  '        -$(DEL) $(CLEAN_FILES)',#010+
   'endif'#010+
   'ifdef LIB_NAME'#010+
   '        -$(DEL) $(LIB_NAME) $(LIB_FULLNAME)'#010+
   'endif'#010+
   '        -$(DEL) $(FPCMADE) *$(FULL_TARGET).fpm Package.fpc *$(ASMEXT)'#010+
-  '        -$(DEL) $(FPCEXTFILE) $(REDIRFILE) script*.','res link*.res *_s'+
-  'cript.res *_link.res'#010+
-  '        -$(DEL) $(PPAS) *_ppas$(BATCHEXT) ppas$(BATCHEXT) ppaslink$(BA'+
-  'TCHEXT)'#010+
+  '        -$(DEL) $(FPCEXTFILE) $(REDIRFILE) script*.res link*.res *_scr'+
+  'ipt.res *_link.res'#010+
+  '        -','$(DEL) $(PPAS) *_ppas$(BATCHEXT) ppas$(BATCHEXT) ppaslink$('+
+  'BATCHEXT)'#010+
   #010+
   'fpc_cleanall: $(CLEANTARGET)'#010+
   'ifdef CLEANEXEFILES'#010+
   '        -$(DEL) $(CLEANEXEFILES)'#010+
   'endif'#010+
   'ifdef COMPILER_UNITTARGETDIR'#010+
-  'ifdef ','CLEANPPUFILES'#010+
-  '        -$(DEL) $(CLEANPPUFILES)'#010+
+  'ifdef CLEANPPUFILES'#010+
+  '        -$(DEL) $(CLEANPPUFILES)'#010,
   'endif'#010+
   'ifneq ($(CLEANPPULINKFILES),)'#010+
   '        -$(DEL) $(CLEANPPULINKFILES)'#010+
@@ -2171,24 +2186,24 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        -$(DEL) $(addprefix $(UNITTARGETDIRPREFIX),$(CLEANRSTFILES))'#010+
   'endif'#010+
   'endif'#010+
-  'ifdef CLEAN_F','ILES'#010+
+  'ifdef CLEAN_FILES'#010+
   '        -$(DEL) $(CLEAN_FILES)'#010+
   'endif'#010+
-  '        -$(DELTREE) units'#010+
+  '     ','   -$(DELTREE) units'#010+
   '        -$(DELTREE) bin'#010+
   '        -$(DEL) *$(OEXT) *$(LTOEXT) *$(PPUEXT) *$(RSTEXT) *$(ASMEXT) *'+
   '$(STATICLIBEXT) *$(SHAREDLIBEXT) *$(PPLEXT)'#010+
   'ifneq ($(PPUEXT),.ppu)'#010+
-  '        -$(','DEL) *.o *.ppu *.a'#010+
+  '        -$(DEL) *.o *.ppu *.a'#010+
   'endif'#010+
-  '        -$(DELTREE) *$(SMARTEXT)'#010+
+  '        -$(DELTREE) *$','(SMARTEXT)'#010+
   '        -$(DEL) fpcmade.* Package.fpc *.fpm'#010+
   '        -$(DEL) $(FPCEXTFILE) $(REDIRFILE) script*.res link*.res *_scr'+
   'ipt.res *_link.res'#010+
-  '        -$(DEL) $(PPAS) *_ppas$(BATCHEXT) ppas$(B','ATCHEXT) ppaslink$('+
-  'BATCHEXT)'#010+
+  '        -$(DEL) $(PPAS) *_ppas$(BATCHEXT) ppas$(BATCHEXT) ppaslink$(BA'+
+  'TCHEXT)'#010+
   'ifdef AOUTEXT'#010+
-  '        -$(DEL) *$(AOUTEXT)'#010+
+  '    ','    -$(DEL) *$(AOUTEXT)'#010+
   'endif'#010+
   'ifdef DEBUGSYMEXT'#010+
   '        -$(DEL) *$(DEBUGSYMEXT)'#010+
@@ -2198,126 +2213,125 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '        -$(DEL) $(FPMAKEBINOBJ)'#010+
   'endif'#010+
   #010+
-  'fpc_distclean',': cleanall'#010+
+  'fpc_distclean: cleanall'#010+
   #010+
   #010+
   '[baseinforules]'#010+
-  '#####################################################################'#010+
+  '##################','##################################################'+
+  '#'#010+
   '# Base info rules'#010+
   '#####################################################################'#010+
   #010+
   '.PHONY: fpc_baseinfo'#010+
   #010+
-  'override INFORULES+=fpc_basein','fo'#010+
+  'override INFORULES+=fpc_baseinfo'#010+
   #010+
   'fpc_baseinfo:'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  == Package info =='#010+
+  '        @$(E','CHO)  == Package info =='#010+
   '        @$(ECHO)  Package Name..... $(PACKAGE_NAME)'#010+
   '        @$(ECHO)  Package Version.. $(PACKAGE_VERSION)'#010+
   '        @$(ECHO)'#010+
   '        @$(ECHO)  == Configuration info =='#010+
-  ' ','       @$(ECHO)'#010+
-  '        @$(ECHO)  FPC.......... $(FPC)'#010+
+  '        @$(ECHO)'#010+
+  '        @$(ECHO)  FPC..........',' $(FPC)'#010+
   '        @$(ECHO)  FPC Version.. $(FPC_VERSION)'#010+
   '        @$(ECHO)  Source CPU... $(CPU_SOURCE)'#010+
   '        @$(ECHO)  Target CPU... $(CPU_TARGET)'#010+
   '        @$(ECHO)  Source OS.... $(OS_SOURCE)'#010+
-  ' ','       @$(ECHO)  Target OS.... $(OS_TARGET)'#010+
-  '        @$(ECHO)  Full Source.. $(FULL_SOURCE)'#010+
+  '        @$(ECHO)  Target OS.... $(OS_TARGET)'#010+
+  '   ','     @$(ECHO)  Full Source.. $(FULL_SOURCE)'#010+
   '        @$(ECHO)  Full Target.. $(FULL_TARGET)'#010+
   '        @$(ECHO)  SourceSuffix. $(SOURCESUFFIX)'#010+
   '        @$(ECHO)  TargetSuffix. $(TARGETSUFFIX)'#010+
-  '      ','  @$(ECHO)  FPC fpmake... $(FPCFPMAKE)'#010+
-  '        @$(ECHO)'#010+
+  '        @$(ECHO)  FPC fpmake... $(FPCFPMAKE)'#010+
+  '        ','@$(ECHO)'#010+
   '        @$(ECHO)  == Directory info =='#010+
   '        @$(ECHO)'#010+
   '        @$(ECHO)  Required pkgs... $(REQUIRE_PACKAGES)'#010+
   '        @$(ECHO)'#010+
   '        @$(ECHO)  Basedir......... $(BASEDIR)'#010+
-  '        @$','(ECHO)  FPCDir.......... $(FPCDIR)'#010+
-  '        @$(ECHO)  CrossBinDir..... $(CROSSBINDIR)'#010+
+  '        @$(ECHO)  FPCDir.......... $(FPCDIR)'#010+
+  '        @$(E','CHO)  CrossBinDir..... $(CROSSBINDIR)'#010+
   '        @$(ECHO)  UnitsDir........ $(UNITSDIR)'#010+
   '        @$(ECHO)  PackagesDir..... $(PACKAGESDIR)'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  GCC library..... $(GCCL','IBDIR)'#010+
-  '        @$(ECHO)  Other library... $(OTHERLIBDIR)'#010+
+  '        @$(ECHO)  GCC library..... $(GCCLIBDIR)'#010+
+  '        @$(ECHO)  Other library... $(OTH','ERLIBDIR)'#010+
   '        @$(ECHO)'#010+
   '        @$(ECHO)  == Tools info =='#010+
   '        @$(ECHO)'#010+
   '        @$(ECHO)  As........ $(AS)'#010+
   '        @$(ECHO)  Ld........ $(LD)'#010+
   '        @$(ECHO)  Ar........ $(AR)'#010+
-  '        @','$(ECHO)  Rc........ $(RC)'#010+
+  '        @$(ECHO)  Rc........ $(RC)'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  Mv........ $(MVPROG)'#010+
+  '    ','    @$(ECHO)  Mv........ $(MVPROG)'#010+
   '        @$(ECHO)  Cp........ $(CPPROG)'#010+
   '        @$(ECHO)  Rm........ $(RMPROG)'#010+
   '        @$(ECHO)  GInstall.. $(GINSTALL)'#010+
   '        @$(ECHO)  Echo...... $(ECHO)'#010+
-  '  ','      @$(ECHO)  Shell..... $(SHELL)'#010+
-  '        @$(ECHO)  Date...... $(DATE)'#010+
+  '        @$(ECHO)  Shell..... $(SHELL)'#010+
+  '        @$(','ECHO)  Date...... $(DATE)'#010+
   '        @$(ECHO)  FPCMake... $(FPCMAKE)'#010+
   '        @$(ECHO)  PPUMove... $(PPUMOVE)'#010+
   '        @$(ECHO)  Zip....... $(ZIPPROG)'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  == Object in','fo =='#010+
+  '        @$(ECHO)  == Object info =='#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  Target Loaders........ $(TARGET_LOADERS)'#010+
+  '        @$(ECHO)  Target',' Loaders........ $(TARGET_LOADERS)'#010+
   '        @$(ECHO)  Target Units.......... $(TARGET_UNITS)'#010+
   '        @$(ECHO)  Target Implicit Units. $(TARGET_IMPLICITUNITS)'#010+
-  '        @$(ECHO)  Target Programs...','.... $(TARGET_PROGRAMS)'#010+
-  '        @$(ECHO)  Target Dirs........... $(TARGET_DIRS)'#010+
+  '        @$(ECHO)  Target Programs....... $(TARGET_PROGRAMS)'#010+
+  '        @$(ECHO)  Targe','t Dirs........... $(TARGET_DIRS)'#010+
   '        @$(ECHO)  Target Examples....... $(TARGET_EXAMPLES)'#010+
   '        @$(ECHO)  Target ExampleDirs.... $(TARGET_EXAMPLEDIRS)'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  Cl','ean Units......... $(CLEAN_UNITS)'#010+
-  '        @$(ECHO)  Clean Files......... $(CLEAN_FILES)'#010+
+  '        @$(ECHO)  Clean Units......... $(CLEAN_UNITS)'#010+
+  '        @$(EC','HO)  Clean Files......... $(CLEAN_FILES)'#010+
   '        @$(ECHO)'#010+
   '        @$(ECHO)  Install Units....... $(INSTALL_UNITS)'#010+
   '        @$(ECHO)  Install Files....... $(INSTALL_FILES)'#010+
   '        @$(ECHO)'#010+
-  '      ','  @$(ECHO)  == Install info =='#010+
-  '        @$(ECHO)'#010+
+  '        @$(ECHO)  == Install info =='#010+
+  '        @$(ECHO)',#010+
   '        @$(ECHO)  DateStr.............. $(DATESTR)'#010+
   '        @$(ECHO)  ZipName.............. $(ZIPNAME)'#010+
   '        @$(ECHO)  ZipPrefix............ $(ZIPPREFIX)'#010+
-  '        @$(ECHO)  ZipCrossPrefix.....','.. $(ZIPCROSSPREFIX)'#010+
-  '        @$(ECHO)  ZipSuffix............ $(ZIPSUFFIX)'#010+
+  '        @$(ECHO)  ZipCrossPrefix....... $(ZIPCROSSPREFIX)'#010+
+  '        @$(ECHO)  ZipSuffi','x............ $(ZIPSUFFIX)'#010+
   '        @$(ECHO)  FullZipName.......... $(FULLZIPNAME)'#010+
   '        @$(ECHO)  Install FPC Package.. $(INSTALL_FPCPACKAGE)'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  Install base d','ir..... $(INSTALL_BASEDIR)'#010+
-  '        @$(ECHO)  Install binary dir... $(INSTALL_BINDIR)'#010+
+  '        @$(ECHO)  Install base dir..... $(INSTALL_BASEDIR)'#010+
+  '        @$(ECHO)  In','stall binary dir... $(INSTALL_BINDIR)'#010+
   '        @$(ECHO)  Install library dir.. $(INSTALL_LIBDIR)'#010+
   '        @$(ECHO)  Install units dir.... $(INSTALL_UNITDIR)'#010+
-  '        @$(ECHO)  Install source dir..','. $(INSTALL_SOURCEDIR)'#010+
-  '        @$(ECHO)  Install doc dir...... $(INSTALL_DOCDIR)'#010+
+  '        @$(ECHO)  Install source dir... $(INSTALL_SOURCEDIR)'#010+
+  '        @$(ECHO)  Instal','l doc dir...... $(INSTALL_DOCDIR)'#010+
   '        @$(ECHO)  Install example dir.. $(INSTALL_EXAMPLEDIR)'#010+
   '        @$(ECHO)  Install data dir..... $(INSTALL_DATADIR)'#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  Dis','t destination dir. $(DIST_DESTDIR)'#010+
-  '        @$(ECHO)  Dist zip name........ $(DIST_ZIPNAME)'#010+
+  '        @$(ECHO)  Dist destination dir. $(DIST_DESTDIR)'#010+
+  '        @$(E','CHO)  Dist zip name........ $(DIST_ZIPNAME)'#010+
   '        @$(ECHO)'#010+
   #010+
   '[inforules]'#010+
   '#####################################################################'#010+
   '# Info rules'#010+
-  '####################################','################################'+
-  '#'#010+
+  '#####################################################################'#010+
   #010+
-  '.PHONY: fpc_info'#010+
+  '.PHONY: fpc_','info'#010+
   #010+
   'fpc_info: $(INFORULES)'#010+
   #010+
   '[makefilerules]'#010+
   '#####################################################################'#010+
   '# Rebuild Makefile'#010+
-  '##########################################################','##########'+
-  '#'#010+
+  '#####################################################################'#010+
   #010+
-  '.PHONY: fpc_makefile fpc_makefiles fpc_makefile_sub1 fpc_makefile_sub2'+
-  ' \'#010+
+  '.PHONY: fpc_makefile fpc_makefiles',' fpc_makefile_sub1 fpc_makefile_su'+
+  'b2 \'#010+
   '        fpc_makefile_dirs'#010+
   #010+
   'fpc_makefile:'#010+
@@ -2325,25 +2339,25 @@ const fpcmakeini : array[0..247,1..240] of char=(
   #010+
   'fpc_makefile_sub1:'#010+
   'ifdef TARGET_DIRS'#010+
-  '        $(FPCMAKE) -w -T$','(OS_TARGET) $(addsuffix /Makefile.fpc,$(TAR'+
-  'GET_DIRS))'#010+
+  '        $(FPCMAKE) -w -T$(OS_TARGET) $(addsuffix /Makefile.fpc,$(TARGE'+
+  'T_','DIRS))'#010+
   'endif'#010+
   'ifdef TARGET_EXAMPLEDIRS'#010+
   '        $(FPCMAKE) -w -T$(OS_TARGET) $(addsuffix /Makefile.fpc,$(TARGE'+
   'T_EXAMPLEDIRS))'#010+
   'endif'#010+
   #010+
-  'fpc_makefile_sub2: $(addsuffix _makefile_dirs,$(TARGET_DIRS) $','(TARGE'+
-  'T_EXAMPLEDIRS))'#010+
+  'fpc_makefile_sub2: $(addsuffix _makefile_dirs,$(TARGET_DIRS) $(TARGET_'+
+  'EXAMPLEDIRS))'#010+
   #010+
-  'fpc_makefile_dirs: fpc_makefile_sub1 fpc_makefile_sub2'#010+
+  'fpc_makefile_dirs: fpc_m','akefile_sub1 fpc_makefile_sub2'#010+
   #010+
   'fpc_makefiles: fpc_makefile fpc_makefile_dirs'#010+
   #010+
   '[localmakefile]'#010+
   '#####################################################################'#010+
   '# Local Makefile'#010+
-  '###########','#########################################################'+
+  '##########################################################','##########'+
   '#'#010+
   #010+
   'ifneq ($(wildcard fpcmake.loc),)'#010+
@@ -2354,8 +2368,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '[userrules]'#010+
   '#####################################################################'#010+
   '# Users rules'#010+
-  '#######################','#############################################'+
-  '#'#010+
+  '#####################################################################'#010,
   #010+
   '[lclrules]'#010+
   '#####################################################################'#010+
@@ -2363,8 +2376,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '#####################################################################'#010+
   #010+
   '# LCL Platform'#010+
-  'ifndef LCL_PL','ATFORM'#010+
-  'ifneq ($(findstring $(OS_TARGET),win32 win64),)'#010+
+  'ifndef LCL_PLATFORM'#010+
+  'ifneq ($(findstring $(OS_TARGET),win32 w','in64),)'#010+
   'LCL_PLATFORM=win32'#010+
   'else'#010+
   'LCL_PLATFORM=gtk'#010+
@@ -2375,8 +2388,8 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Check if the specified LCLDIR is correct'#010+
   'ifdef LCLDIR'#010+
   'override LCLDIR:=$(subst \,/,$(LCLDIR))'#010+
-  'ifeq ($(wildcar','d $(LCLDIR)/units/$(LCL_PLATFORM)),)'#010+
-  'override LCLDIR=wrong'#010+
+  'ifeq ($(wildcard $(LCLDIR)/units/$(LCL_PLATFORM)),)'#010+
+  'override L','CLDIR=wrong'#010+
   'endif'#010+
   'else'#010+
   'override LCLDIR=wrong'#010+
@@ -2385,26 +2398,26 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '# Check if the default LCLDIR is correct'#010+
   'ifdef DEFAULT_LCLDIR'#010+
   'override LCLDIR:=$(subst \,/,$(DEFAULT_LCLDIR))'#010+
-  'ifeq ($(wildcard $(LCLDIR)/unit','s/$(LCL_PLATFORM)),)'#010+
+  'ifeq ($(wildcard $(LCLDIR)/units/$(LCL_PLATFORM)),)'#010+
   'override LCLDIR=wrong'#010+
-  'endif'#010+
+  'endi','f'#010+
   'endif'#010+
   #010+
   '# Check for development version'#010+
   'ifeq ($(LCLDIR),wrong)'#010+
   'override LCLDIR=$(subst /units/$(LCL_PLATFORM),,$(firstword $(wildcard'+
-  ' $(addsuffix /units/$(LCL_PLATFORM),$(BASEDIR)/lcl $(BASEDI','R)))))'#010+
+  ' $(addsuffix /units/$(LCL_PLATFORM),$(BASEDIR)/lcl $(BASEDIR)))))'#010+
   'ifeq ($(LCLDIR),)'#010+
-  'override LCLDIR=wrong'#010+
+  'override LCLDIR=wrong'#010,
   'endif'#010+
   'endif'#010+
   #010+
   '# Check for release version'#010+
   'ifeq ($(LCLDIR),wrong)'#010+
   'override LCLDIR=$(subst /units/$(LCL_PLATFORM),,$(firstword $(wildcard'+
-  ' $(addsuffix /lib/lazarus/units/$(LCL_PLATFORM),/usr/local ','/usr))))'#010+
+  ' $(addsuffix /lib/lazarus/units/$(LCL_PLATFORM),/usr/local /usr))))'#010+
   'ifeq ($(LCLDIR),)'#010+
-  'override LCLDIR=wrong'#010+
+  'override LCLDIR=wron','g'#010+
   'endif'#010+
   'endif'#010+
   #010+
@@ -2412,18 +2425,18 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'override LCLUNITDIR=$(wildcard $(LCLDIR)/units/$(LCL_PLATFORM) $(LCLDI'+
   'R)/units)'#010+
   'override LCLCOMPONENTDIR=$(wildcard $(LCLDIR)/.. $(LCLDIR)/../componen'+
-  'ts $(LCLDIR)','/components)'#010+
-  'export LCLDIR LCLUNITDIR LCLCOMPONENTDIR'#010+
+  'ts $(LCLDIR)/components)'#010+
+  'export LCLDIR LCLUNITDIR LCLCOMPON','ENTDIR'#010+
   #010+
   '# Add LCL dirs to paths'#010+
   'override REQUIRE_PACKAGESDIR+=$(LCLCOMPONENTDIR)'#010+
   'override COMPILER_UNITDIR+=$(LCLUNITDIR)'#010+
   #010+
   '[lclinforules]'#010+
-  '#######################################################','#############'+
-  '#'#010+
-  '# LCL Info rules'#010+
   '#####################################################################'#010+
+  '# LCL Info rules'#010+
+  '###############','#####################################################'+
+  '#'#010+
   'override INFORULES+=lclinfo'#010+
   #010+
   '.PHONY: lclinfo'#010+
@@ -2431,23 +2444,23 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'lclinfo:'#010+
   '        @$(ECHO)  == LCL info =='#010+
   '        @$(ECHO)'#010+
-  '        @$(ECHO)  Platform.......','...... $(LCL_PLATFORM)'#010+
-  '        @$(ECHO)  LCLDIR............... $(LCLDIR)'#010+
+  '        @$(ECHO)  Platform............. $(LCL_PLATFORM)'#010+
+  '        @$(ECHO)  LCLDIR','............... $(LCLDIR)'#010+
   '        @$(ECHO)  LCL Unit dir......... $(LCLUNITDIR)'#010+
   '        @$(ECHO)  LCL Component dir.... $(LCLCOMPONENTDIR)'#010+
   '        @$(ECHO)'#010+
   #010+
   '[fpmakeprerules]'#010+
-  '###################','#################################################'+
+  '##################################################################','##'+
   '#'#010+
   '# fpmake prerules'#010+
   '#####################################################################'#010+
   'FPMAKEBIN=fpmake$(SRCEXEEXT)'#010+
   'FPMAKEBINOBJ=fpmake$(OEXT) fpmake$(LTOEXT)'#010+
-  'LOCALFPMAKEBIN=.$(PATHSEP)$(F','PMAKEBIN)'#010+
+  'LOCALFPMAKEBIN=.$(PATHSEP)$(FPMAKEBIN)'#010+
   #010+
-  '# Convert the OS_TARGET and CPU_TARGET options to fpmake'#039's --os an'+
-  'd --cpu parameters'#010+
+  '# Convert the OS_TARGET and CPU_TARG','ET options to fpmake'#039's --os '+
+  'and --cpu parameters'#010+
   'ifdef OS_TARGET'#010+
   'FPC_TARGETOPT+=--os=$(OS_TARGET)'#010+
   'endif'#010+
@@ -2455,65 +2468,66 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'FPC_TARGETOPT+=--cpu=$(CPU_TARGET)'#010+
   'endif'#010+
   #010+
-  '# Get the location of the boot','strap-fpmkunit units'#010+
-  'PACKAGEDIR_FPMKUNIT:=$(firstword $(subst /Makefile.fpc,,$(strip $(wild'+
-  'card $(addsuffix /fpmkunit/Makefile.fpc,$(PACKAGESDIR))))))'#010+
+  '# Get the location of the bootstrap-fpmkunit units'#010+
+  'PACKAGEDIR_FPMKUNIT:=$(fir','stword $(subst /Makefile.fpc,,$(strip $(wi'+
+  'ldcard $(addsuffix /fpmkunit/Makefile.fpc,$(PACKAGESDIR))))))'#010+
   'ifneq ($(PACKAGEDIR_FPMKUNIT),)'#010+
-  'UNITDIR_FPMAKE_FPMKUNIT=$(PACKAGEDIR_FPMKUNIT)/units_bs/$','(SOURCESUFF'+
-  'IX)'#010+
-  'override COMPILER_FPMAKE_UNITDIR=$(UNITDIR_FPMAKE_FPMKUNIT)'#010+
+  'UNITDIR_FPMAKE_FPMKUNIT=$(PACKAGEDIR_FPMKUNIT)/units_bs/$(SOURCESUFFIX'+
+  ')'#010+
+  'override COMPILER_FPMAKE_UNITDIR','=$(UNITDIR_FPMAKE_FPMKUNIT)'#010+
   'FPMKUNIT_SRC=$(PACKAGEDIR_FPMKUNIT)/src/fpmkunit.pp'#010+
   'FPMKUNIT_PPU=$(UNITDIR_FPMAKE_FPMKUNIT)/fpmkunit.ppu'#010+
   'endif'#010+
   #010+
   'ifdef FPMAKE_SKIP_CONFIG'#010+
-  'override FPMAKE_BUILD_OPT+=$','(FPMAKE_SKIP_CONFIG)'#010+
+  'override FPMAKE_BUILD_OPT+=$(FPMAKE_SKIP_CONFIG)'#010+
   'endif'#010+
   #010+
   '[fpmakerules]'#010+
-  '#####################################################################'#010+
+  '#####','###############################################################'+
+  '#'#010+
   '# fpmake rules'#010+
   '#####################################################################'#010+
-  '.PHONY: fpc_fpmake fpc_fpmake_clean fpc_fpm','ake_install fpc_fpmake_ex'+
-  'ampleinstall'#010+
+  '.PHONY: fpc_fpmake fpc_fpmake_clean fpc_fpmake_install fpc_fpmake_exam'+
+  'pleinstall'#010+
   #010+
-  '# Do not pass the Makefile'#039's unit and binary target locations. fpm'+
-  'ake uses it'#039's own.'#010+
+  '# Do not',' pass the Makefile'#039's unit and binary target locations. f'+
+  'pmake uses it'#039's own.'#010+
   'override FPCOPT:=$(filter-out -FU%,$(FPCOPT))'#010+
   'override FPCOPT:=$(filter-out -FE%,$(FPCOPT))'#010+
-  '# Compose general fpmake','-parameters'#010+
+  '# Compose general fpmake-parameters'#010+
   'ifdef FPMAKEOPT'#010+
-  'FPMAKE_OPT+=$(FPMAKEOPT)'#010+
+  'FPMAKE_OPT+=$(FPMAK','EOPT)'#010+
   'endif'#010+
   'FPMAKE_OPT+=--localunitdir=$(FPCDIR)'#010+
   'FPMAKE_OPT+=--globalunitdir=$(FPCDIR)/packages'#010+
   'FPMAKE_OPT+=$(FPC_TARGETOPT)'#010+
   'FPMAKE_OPT+=$(addprefix -o ,$(FPCOPT))'#010+
-  'FPMAKE_OPT+=--compiler=$(FPC)',#010+
+  'FPMAKE_OPT+=--compiler=$(FPC)'#010+
   'FPMAKE_OPT+=-bu'#010+
   #010+
-  'FPMAKE_INSTALL_OPT+=--unitinstalldir=$(INSTALL_UNITDIR)'#010+
+  'FPMAKE_INSTALL_OPT+=--unitins','talldir=$(INSTALL_UNITDIR)'#010+
   'ifdef UNIXHier'#010+
   'FPMAKE_INSTALL_OPT+=--prefix=$(INSTALL_PREFIX)'#010+
   'FPMAKE_INSTALL_OPT+=--baseinstalldir=$(INSTALL_LIBDIR)/fpc/$(FPC_VERSI'+
   'ON)'#010+
   'else'#010+
-  'FPMAKE_INSTALL_OPT+=--pre','fix=$(INSTALL_BASEDIR)'#010+
+  'FPMAKE_INSTALL_OPT+=--prefix=$(INSTALL_BASEDIR)'#010+
   'endif'#010+
   #010+
-  'override ALLTARGET+=fpc_fpmake'#010+
+  'override ALLTARGE','T+=fpc_fpmake'#010+
   'override INSTALLTARGET+=fpc_fpmake_install'#010+
   'override EXAMPLEINSTALLTARGET+=fpc_fpmake_exampleinstall'#010+
   '# If no fpmake exists and (dist)clean is called, do not try to build f'+
-  'pmake, it',' will'#010+
-  '# most often fail because the dependencies are cleared.'#010+
+  'pmake, it will'#010+
+  '# most often fail because the dependencie','s are cleared.'#010+
   '# In case of a clean, simply do nothing'#010+
   'ifneq ($(wildcard $(LOCALFPMAKEBIN)),)'#010+
   'override CLEANTARGET+=fpc_fpmake_clean'#010+
   'endif'#010+
   #010+
   '$(FPMKUNIT_PPU): $(FPMKUNIT_SRC)'#010+
-  '            $(MAKE) ','-C $(PACKAGEDIR_FPMKUNIT) bootstrap $(addprefix '+
+  '            $(MAKE) -C $(PACKAGEDIR_FPMKUNIT) bootstrap $(addprefix',' '+
   'OPT=,$(FPMAKE_BUILD_OPT))'#010+
   #010+
   '$(FPMAKEBIN): fpmake.pp $(FPMKUNIT_PPU)'#010+
@@ -2521,7 +2535,7 @@ const fpcmakeini : array[0..247,1..240] of char=(
   'IR)) $(FPMAKE_BUILD_OPT)'#010+
   #010+
   'fpc_fpmake: $(FPMAKEBIN)'#010+
-  '    ','        $(LOCALFPMAKEBIN) compile $(FPMAKE_OPT)'#010+
+  '            $(LOCALFPMAKEBIN) compile $(FPMAKE_OPT)',#010+
   #010+
   'fpc_fpmake_clean: $(FPMAKEBIN)'#010+
   '            $(LOCALFPMAKEBIN) clean $(FPMAKE_OPT)'#010+
@@ -2530,12 +2544,12 @@ const fpcmakeini : array[0..247,1..240] of char=(
   '            $(LOCALFPMAKEBIN) install $(FPMAKE_OPT) $(FPMAKE_INSTALL_O'+
   'PT)'#010+
   #010+
-  '#',' This is not completely valid. Exampleinstall should only install t'+
+  '# This is not completely valid. Exampleinstall s','hould only install t'+
   'he examples, while'#010+
   '# fpmake -ie installs everything, including the examples. This also me'+
   'ans that on'#010+
   '# a distinstall fpmake install wil be called twice.'#010+
-  'fpc_fpmake_examplein','stall: $(FPMAKEBIN)'#010+
-  '            $(LOCALFPMAKEBIN) install -ie $(FPMAKE_OPT) $(FPMAKE_INSTA'+
-  'LL_OPT)'#010
+  'fpc_fpmake_exampleinstall: $(FPMAKEBIN)'#010+
+  '            $(LOCALFPMAKEBI','N) install -ie $(FPMAKE_OPT) $(FPMAKE_INS'+
+  'TALL_OPT)'#010
 );
diff --git a/utils/fpcm/fpcmake.ini b/utils/fpcm/fpcmake.ini
index 16396ca921..fa2b61a31e 100644
--- a/utils/fpcm/fpcmake.ini
+++ b/utils/fpcm/fpcmake.ini
@@ -295,6 +295,20 @@ endif
 override FPCOPT+=-Cp$(SUBARCH)
 endif
 
+ifeq ($(FULL_TARGET),xtensa-freertos)
+ifeq ($(SUBARCH),)
+$(error When compiling for xtensa-freertos, a sub-architecture (e.g. SUBARCH=lx106 or SUBARCH=lx6) must be defined)
+endif
+override FPCOPT+=-Cp$(SUBARCH)
+endif
+
+ifeq ($(FULL_TARGET),arm-freertos)
+ifeq ($(SUBARCH),)
+$(error When compiling for arm-freertos, a sub-architecture (e.g. SUBARCH=armv6m or SUBARCH=armv7em) must be defined)
+endif
+override FPCOPT+=-Cp$(SUBARCH)
+endif
+
 # Full name of the target, including CPU and OS. For OSs limited
 # to 8.3 we only use the target OS
 ifneq ($(findstring $(OS_SOURCE),$(LIMIT83fs)),)
diff --git a/utils/fpcm/fpcmmain.pp b/utils/fpcm/fpcmmain.pp
index a7e81ce31b..a9a71440a5 100644
--- a/utils/fpcm/fpcmmain.pp
+++ b/utils/fpcm/fpcmmain.pp
@@ -155,7 +155,7 @@ interface
         {dragonfly} ( false, false, false, false, true,  false, false, false, false, false, false, false, false, false,   false, false, false, false, false, false,  false,   false),
         { win16 }   ( false, false, false, false, false, false, false, false, false, false, false, false, false, false,   false, true , false, false, false, false,  false,   false),
         { wasm }    ( false, false, false, false, false, false, false, false, false, false, false, false, false, false,   false, false, false, true,  false, false,  false,   false),
-        { freertos }( false, false, false, false, false, false, false, false, false, false, false, false, false, false,   false, false, false, false, false, false,  false,   true )
+        { freertos }( false, false, false, false, false, true,  false, false, false, false, false, false, false, false,   false, false, false, false, false, false,  false,   true )
       );
 
     type
